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authorBiju Das <biju.das@bp.renesas.com>2019-06-12 17:20:53 +0300
committerSimon Horman <horms+renesas@verge.net.au>2019-06-18 13:42:02 +0300
commit5f5249497bd7ed65d90cac36c3c3dabcda2903dd (patch)
tree3c702542b17665544f4f00a18e5d671d1445d268 /drivers/fpga/fpga-mgr.c
parent7b996955e514bd3639419c1e725bc3b69c96bd05 (diff)
downloadlinux-5f5249497bd7ed65d90cac36c3c3dabcda2903dd.tar.xz
arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhz
Set the capacity-dmips-mhz for RZ/G2M(r8a774a1) SoC, that is based on dhrystone. Based on work done by Gaku Inami <gaku.inami.xw@bp.renesas.com> for r8a7796 SoC. The average dhrystone result for 5 iterations is as below: r8a774a1 SoC (CA57x2 + CA53x4) CPU max-freq dhrystone --------------------------------- CA57 1500 MHz 11428571 lps/s CA53 1200 MHz 5000000 lps/s From this, CPU capacity-dmips-mhz for CA57 and CA53 are calculated as follows: r8a774a1 SoC CA57 : 1024 / (11428571 / 1500) * (11428571 / 1500) = 1024 CA53 : 1024 / (11428571 / 1500) * ( 5000000 / 1200) = 560 Since each CPUs have different max frequencies, the final CPU capacities of A53 scaled by the above difference is as below $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 448 448 448 448 Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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