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| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-20 21:21:37 +0300 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-20 22:12:15 +0300 |
| commit | 66569052fe5328729ff696c1ec17913907d00b5f (patch) | |
| tree | 4350bd64bf5b1297a5b1bf42123fc5134c7aaffb /drivers/fpga/fpga-bridge.c | |
| parent | 65da7d1979c229b69d3fbec63350a6ae26232ad6 (diff) | |
| download | linux-66569052fe5328729ff696c1ec17913907d00b5f.tar.xz | |
irqchip/gic-v3: Don't try to reset AP0Rn
Clearing AP0Rn has created a number of regressions, due to systems
that have SCR_EL3.FIQ set. Even when addressing some obvious bugs,
GIC500 platforms seem to act bizarrely (we are supposed to have
5 bits of priority, but PMR seems to behave as if we had 6...).
Drop the AP0Rn reset for the time being, it is unlikely to have any
effect if kexec-ing.
Fixes: d6062a6d62c6 irqchip/gic-v3: Reset APgRn registers at boot time
Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions