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| author | Stefan Agner <stefan@agner.ch> | 2018-04-18 15:49:08 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-05-16 01:41:01 +0300 |
| commit | 2e5be528ab0182ad4b42b9feea3b80f85f37179b (patch) | |
| tree | b3852d07d5f178c6918736136dbfbb69a6ff218c /drivers/fpga/fpga-bridge.c | |
| parent | c964cfc612b59910593fa10ee1c2673db274c9c7 (diff) | |
| download | linux-2e5be528ab0182ad4b42b9feea3b80f85f37179b.tar.xz | |
clk: imx6ull: use OSC clock during AXI rate change
On i.MX6 ULL using PLL3 seems to cause a freeze when setting
the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear
since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag
for busy divider and busy mux"), probably because the clock is
now forced to be on.
Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions