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| author | Charles Perry <charles.perry@savoirfairelinux.com> | 2024-03-22 01:04:35 +0300 |
|---|---|---|
| committer | Xu Yilun <yilun.xu@linux.intel.com> | 2024-03-31 17:44:21 +0300 |
| commit | 104712a0866f7e3eb050271fc104c543aac642e8 (patch) | |
| tree | 40bfda05cbf771f551c616945d538201453feebb /drivers/fpga/Makefile | |
| parent | 8afcb190f3aac8d9ae4ca4f84a67bb281a4d9a3f (diff) | |
| download | linux-104712a0866f7e3eb050271fc104c543aac642e8.tar.xz | |
fpga: xilinx-selectmap: add new driver
Xilinx 7 series FPGA can be programmed using a parallel port named
the SelectMAP interface in the datasheet. This interface is compatible
with the i.MX6 EIM bus controller but other types of external memory
mapped parallel bus might work.
xilinx-selectmap currently only supports the x8 mode where data is loaded
at one byte per rising edge of the clock, with the MSb of each byte
presented to the D0 pin.
Signed-off-by: Charles Perry <charles.perry@savoirfairelinux.com>
[yilun.xu@linux.intel.com: replace data type of i from u32 to size_t]
Acked-by: Xu Yilun <yilun.xu@intel.com>
Link: https://lore.kernel.org/r/20240321220447.3260065-4-charles.perry@savoirfairelinux.com
Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
Diffstat (limited to 'drivers/fpga/Makefile')
| -rw-r--r-- | drivers/fpga/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 7ec795b6a5a7..aeb89bb13517 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o +obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o |