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authorAmit Vadhavana <av2082000@gmail.com>2024-08-31 20:29:49 +0300
committerVinod Koul <vkoul@kernel.org>2024-09-02 11:26:01 +0300
commita688efea0f2a084aee372e5b7b12d4d2d172f99a (patch)
tree5604867da1803c5f49f3997eed56a3e6ac20f356 /drivers/dma/lgm
parent5d318b5959824e15d32f19b2224c69da89e98178 (diff)
downloadlinux-a688efea0f2a084aee372e5b7b12d4d2d172f99a.tar.xz
dmaengine: Fix spelling mistakes
Correct spelling mistakes in the DMA engine to improve readability and clarity without altering functionality. Signed-off-by: Amit Vadhavana <av2082000@gmail.com> Reviewed-by: Kees Cook <kees@kernel.org> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/r/20240831172949.13189-1-av2082000@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/dma/lgm')
-rw-r--r--drivers/dma/lgm/lgm-dma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/lgm/lgm-dma.c b/drivers/dma/lgm/lgm-dma.c
index 4117c7b67e9c..8173c3f1075a 100644
--- a/drivers/dma/lgm/lgm-dma.c
+++ b/drivers/dma/lgm/lgm-dma.c
@@ -107,7 +107,7 @@
* If header mode is set in DMA descriptor,
* If bit 30 is disabled, HDR_LEN must be configured according to channel
* requirement.
- * If bit 30 is enabled(checksum with heade mode), HDR_LEN has no need to
+ * If bit 30 is enabled(checksum with header mode), HDR_LEN has no need to
* be configured. It will enable check sum for switch
* If header mode is not set in DMA descriptor,
* This register setting doesn't matter