diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2023-12-22 01:03:58 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-12-23 02:31:52 +0300 |
| commit | 14a6960b3e928ccea22d687fb0626237885a20bd (patch) | |
| tree | cf1299d83cdee5389509486f74241460b04fad9d /drivers/cxl/cxl.h | |
| parent | 1037b82fccfe9c001ffa7a883651bb4cde7b705c (diff) | |
| download | linux-14a6960b3e928ccea22d687fb0626237885a20bd.tar.xz | |
cxl: Add helper function that calculate performance data for downstream ports
The CDAT information from the switch, Switch Scoped Latency and Bandwidth
Information Structure (SSLBIS), is parsed and stored under a cxl_dport
based on the correlated downstream port id from the SSLBIS entry. Walk
the entire CXL port paths and collect all the performance data. Also
pick up the link latency number that's stored under the dports. The
entire path PCIe bandwidth can be retrieved using the
pcie_bandwidth_available() call.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/170319623824.2212653.10302079766473698427.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
| -rw-r--r-- | drivers/cxl/cxl.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index dd234f3b9ed4..492dbf63935f 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -876,6 +876,9 @@ static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) void cxl_endpoint_parse_cdat(struct cxl_port *port); void cxl_switch_parse_cdat(struct cxl_port *port); +int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, + struct access_coordinate *coord); + /* * Unit test builds overrides this to __weak, find the 'strong' version * of these symbols in tools/testing/cxl/. |