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authorAndrew Chew <achew@nvidia.com>2013-08-07 15:25:09 +0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2013-11-26 20:43:58 +0400
commit897e1dde1ec1571a28545594633624927fa0a76e (patch)
treec7832c368645e80a3da98082cc13f8c2208a6028 /drivers/clk
parent252d0d2bb07119296e215de7dc9afa8d12746b80 (diff)
downloadlinux-897e1dde1ec1571a28545594633624927fa0a76e.tar.xz
clk: tegra: Set the clk parent of host1x to pll_p
The power-on default parent for this clock is pll_m, which turns out to be wrong. Previously, bootloader reparented this clock. We'll do it in the kernel as well, so that there's one less thing that we depend on bootloader to initialize. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/clk-tegra114.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index e3904923005b..9b8c938477de 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -2183,6 +2183,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
{TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
{TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
+ {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
{TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
{TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
{TEGRA114_CLK_GR_2D, TEGRA114_CLK_PLL_C2, 300000000, 0},