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author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-11-08 20:12:34 +0300 |
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committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-01-23 13:44:27 +0300 |
commit | e66f81bbd7464621215219b72a0523f1b1078fae (patch) | |
tree | 92a3d993ca4999754bc512a66a3830577bde95d3 /drivers/clk/sunxi-ng/ccu_nm.c | |
parent | d77e8135b3405dd08a6bf05613d765cbd0bfd5a6 (diff) | |
download | linux-e66f81bbd7464621215219b72a0523f1b1078fae.tar.xz |
clk: sunxi-ng: Implement factors offsets
The factors we've seen so far all had an offset of one. However, on the
earlier Allwinner SoCs, some factors could have no offset at all, meaning
that the value computed to reach the rate we want to use was the one we had
to program in the registers.
Implement an additional field for the factors that can have such an offset
(linears, not based on a power of two) to specify that offset.
This offset is not linked to the extremums that can be specified in those
structures too. The minimum and maximum are representing the range of
values we can use to try to compute the best rate. The offset comes later
on when we want to set the best value in the registers.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_nm.c')
-rw-r--r-- | drivers/clk/sunxi-ng/ccu_nm.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c index c9f3b6c982f0..158d74e0215f 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.c +++ b/drivers/clk/sunxi-ng/ccu_nm.c @@ -80,11 +80,17 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw, n = reg >> nm->n.shift; n &= (1 << nm->n.width) - 1; + n += nm->n.offset; + if (!n) + n++; m = reg >> nm->m.shift; m &= (1 << nm->m.width) - 1; + m += nm->m.offset; + if (!m) + m++; - return parent_rate * (n + 1) / (m + 1); + return parent_rate * n / m; } static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, @@ -129,8 +135,9 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); - writel(reg | ((_nm.m - 1) << nm->m.shift) | ((_nm.n - 1) << nm->n.shift), - nm->common.base + nm->common.reg); + reg |= (_nm.n - nm->n.offset) << nm->n.shift; + reg |= (_nm.m - nm->m.offset) << nm->m.shift; + writel(reg, nm->common.base + nm->common.reg); spin_unlock_irqrestore(nm->common.lock, flags); |