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| author | Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2018-11-29 03:39:49 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-12-07 13:45:06 +0300 |
| commit | 36c4da4f552a126bb29a95dc5c9608795491e32a (patch) | |
| tree | 68b1032563ac247bd884b8e64cb258d0fbe688a5 /drivers/clk/renesas/r8a77990-cpg-mssr.c | |
| parent | e2f4dd1f5b51b4dab813aa6e4db44e87aa750393 (diff) | |
| download | linux-36c4da4f552a126bb29a95dc5c9608795491e32a.tar.xz | |
clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
On H3 (ES1.x, ES2.0) and M3-W (ES1.0, ES1.1) the clock setting for HS400
needs a quirk to function properly. The reason for the quirk is that
there are two settings which produces same divider value for the SDn
clock. On the effected boards the one currently selected results in
HS400 not working.
This change uses the same method as the Gen2 CPG driver and simply
ignores the first clock setting as this is the offending one when
selecting the settings. Which of the two possible settings is used have
no effect for SDR104.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a77990-cpg-mssr.c')
0 files changed, 0 insertions, 0 deletions