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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2021-07-14 02:25:06 +0300 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2021-09-23 12:46:37 +0300 |
| commit | 9e544b75b20f7e9e7767acc11b46fd38b4989eb4 (patch) | |
| tree | b296b744bbefc2ad52ab12e7fcf3a7a48156aba9 /drivers/clk/meson/meson8b.h | |
| parent | 1792bdac34a7bc79c2086508b3a1644db2088fbc (diff) | |
| download | linux-9e544b75b20f7e9e7767acc11b46fd38b4989eb4.tar.xz | |
clk: meson: meson8b: Add the vid_pll_lvds_en gate clock
HHI_VID_DIVIDER_CNTL[11] must be enabled for the video clock tree to
work. This bit is described as "LVDS_CLK_EN". It is not 100% clear where
this bit has to be placed in the hierarchy. But since the "LVDS_OUT" of
the HDMI PLL uses it's own set of registers it's more likely that this
"LVDS_CLK_EN" bit actually enables the input of the "hdmi_pll_lvds_out"
clock to the "vid_pll_in_sel" tree.
Add a gate definition for this bit (which will not be exported) so that
the kernel can manage all required bits to enable and disable the video
clocks.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20210713232510.3057750-3-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/clk/meson/meson8b.h')
| -rw-r--r-- | drivers/clk/meson/meson8b.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index c764143e2617..b90c21bbd907 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -172,8 +172,9 @@ #define CLKID_CTS_MCLK_I958_DIV 211 #define CLKID_VCLK_EN 214 #define CLKID_VCLK2_EN 215 +#define CLKID_VID_PLL_LVDS_EN 216 -#define CLK_NR_CLKS 216 +#define CLK_NR_CLKS 217 /* * include the CLKID and RESETID that have |