diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-19 14:21:44 +0300 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 12:09:56 +0300 |
| commit | 513b67ac39b0ef91761d94d1d6e31bb84e380744 (patch) | |
| tree | a9b7add7308b61715accd57b598a8f426c8860e6 /drivers/clk/meson/axg.h | |
| parent | 093c3fac4619d267136dc4cb87b916c692fa07db (diff) | |
| download | linux-513b67ac39b0ef91761d94d1d6e31bb84e380744.tar.xz | |
clk: meson: add mpll pre-divider
mpll clocks parent can actually be divided by 1 or 2. So far, this
divider has always been set to 1, so the calculation was correct.
Now that we know it exists, model the tree correctly. If we ever get
a platform where the divider is different, we won't get into trouble
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.h')
| -rw-r--r-- | drivers/clk/meson/axg.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 4916c7045c48..6e5dc65041b5 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -121,8 +121,9 @@ #define CLKID_MPLL1_DIV 66 #define CLKID_MPLL2_DIV 67 #define CLKID_MPLL3_DIV 68 +#define CLKID_MPLL_PREDIV 70 -#define NR_CLKS 70 +#define NR_CLKS 71 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/axg-clkc.h> |