From 513b67ac39b0ef91761d94d1d6e31bb84e380744 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 19 Feb 2018 12:21:44 +0100 Subject: clk: meson: add mpll pre-divider mpll clocks parent can actually be divided by 1 or 2. So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, model the tree correctly. If we ever get a platform where the divider is different, we won't get into trouble Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- drivers/clk/meson/axg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk/meson/axg.h') diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 4916c7045c48..6e5dc65041b5 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -121,8 +121,9 @@ #define CLKID_MPLL1_DIV 66 #define CLKID_MPLL2_DIV 67 #define CLKID_MPLL3_DIV 68 +#define CLKID_MPLL_PREDIV 70 -#define NR_CLKS 70 +#define NR_CLKS 71 /* include the CLKIDs that have been made part of the DT binding */ #include -- cgit v1.2.3