diff options
| author | Paul Cercueil <paul@crapouillou.net> | 2019-05-03 00:24:58 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-06-07 21:48:58 +0300 |
| commit | a9fa2893fcc64bd32cbc46bfb7aa09bde8175987 (patch) | |
| tree | d8d53fdece53eaef53440ecb0828626edae9c9e5 /drivers/clk/ingenic/cgu.h | |
| parent | a188339ca5a396acc588e5851ed7e19f66b0ebd9 (diff) | |
| download | linux-a9fa2893fcc64bd32cbc46bfb7aa09bde8175987.tar.xz | |
clk: ingenic: Add support for divider tables
Some clocks provided on Ingenic SoCs have dividers, whose hardware value
as written in the register cannot be expressed as an affine function
to the actual divider value.
For instance, for the CPU clock on the JZ4770, the dividers are coded as
follows:
------------------
| Bits | Div |
------------------
| 0 0 0 | 1 |
| 0 0 1 | 2 |
| 0 1 0 | 3 |
| 0 1 1 | 4 |
| 1 0 0 | 6 |
| 1 0 1 | 8 |
| 1 1 0 | 12 |
------------------
To support this setup, we introduce a new field in the
ingenic_cgu_div_info structure that allows to specify the divider table.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/cgu.h')
| -rw-r--r-- | drivers/clk/ingenic/cgu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index e12716d8ce3c..8dcd83aeab84 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -88,6 +88,8 @@ struct ingenic_cgu_mux_info { * isn't one * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one + * @div_table: optional table to map the value read from the register to the + * actual divider value */ struct ingenic_cgu_div_info { unsigned reg; @@ -97,6 +99,7 @@ struct ingenic_cgu_div_info { s8 ce_bit; s8 busy_bit; s8 stop_bit; + const u8 *div_table; }; /** |