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authorAbhishek Sahu <absahu@codeaurora.org>2018-06-20 10:27:30 +0300
committerMiquel Raynal <miquel.raynal@bootlin.com>2018-07-18 10:24:05 +0300
commitc168ac273ce34b8fb181b230544c4eac80f55b9f (patch)
tree169e3c5be3f5611a7868056b31098c8abdcce512 /crypto/sm3_generic.c
parentf9801fda963ec9d0f6521695d2b0158249d85c94 (diff)
downloadlinux-c168ac273ce34b8fb181b230544c4eac80f55b9f.tar.xz
dt-bindings: qcom_nandc: update for ECC strength and step size
1. If nand-ecc-strength specified in DT, then controller will use this ECC strength otherwise ECC strength will be calculated according to chip requirement and available OOB size. 2. QCOM NAND controller supports only one step size (512 bytes) but nand-ecc-step-size is required property in DT. This DT property can be removed and ecc step size can be assigned in driver with 512 bytes value. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'crypto/sm3_generic.c')
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