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| author | Zenghui Yu <yuzenghui@huawei.com> | 2020-03-04 23:33:11 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-03-20 20:48:09 +0300 |
| commit | b978c25f6ee7d4c79cbe918eed684e53887ec001 (patch) | |
| tree | 557379c4648fe28c79a19a9653613fcea9c3f7b5 /crypto/async_tx/async_xor.c | |
| parent | f3a059219bc718ccc3bf3ff894f089b7e9a93139 (diff) | |
| download | linux-b978c25f6ee7d4c79cbe918eed684e53887ec001.tar.xz | |
irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation
In GICv4.1, we emulate a guest-issued INVALL command by a direct write
to GICR_INVALLR. Before we finish the emulation and go back to guest,
let's make sure the physical invalidate operation is actually completed
and no stale data will be left in redistributor. Per the specification,
this can be achieved by polling the GICR_SYNCR.Busy bit (to zero).
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20200302092145.899-1-yuzenghui@huawei.com
Link: https://lore.kernel.org/r/20200304203330.4967-5-maz@kernel.org
Diffstat (limited to 'crypto/async_tx/async_xor.c')
0 files changed, 0 insertions, 0 deletions