diff options
| author | Linus Walleij <linus.walleij@linaro.org> | 2021-07-19 14:14:16 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2021-08-09 02:55:08 +0300 |
| commit | e647167967f84b95f64c9ff14dc161fbd645e5cc (patch) | |
| tree | 21b0025164ba14ce93c44b54c0d4fda1a2cb0bc2 /arch | |
| parent | 94e8b34be2c0f43da8bc3406bcbf6e459d38b338 (diff) | |
| download | linux-e647167967f84b95f64c9ff14dc161fbd645e5cc.tar.xz | |
ARM: dts: ixp4xx: Add second UART
The IXP4xx has two UARTs and some platforms make use of the
second one so add this to the include DTSI.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/intel-ixp4xx.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index a50427ad05e7..45cb3ad954c1 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -83,6 +83,20 @@ no-loopback-test; }; + uart1: serial@c8001000 { + compatible = "intel,xscale-uart"; + reg = <0xc8001000 0x1000>; + /* + * The reg-offset and reg-shift is a side effect + * of running the platform in big endian mode. + */ + reg-offset = <3>; + reg-shift = <2>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <14745600>; + no-loopback-test; + }; + gpio0: gpio@c8004000 { compatible = "intel,ixp4xx-gpio"; reg = <0xc8004000 0x1000>; |