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| author | Max Filippov <jcmvbkbc@gmail.com> | 2018-12-21 04:18:12 +0300 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-05-07 20:36:31 +0300 |
| commit | f7c34874f04a80d6c39a32f08da2529e59602d3c (patch) | |
| tree | a225ab153205701d24bee7423fc950a9009cb533 /arch/xtensa/include/asm/barrier.h | |
| parent | d065fcf12c21348cbc125460f75332f467518fb1 (diff) | |
| download | linux-f7c34874f04a80d6c39a32f08da2529e59602d3c.tar.xz | |
xtensa: add exclusive atomics support
Implement atomic primitives using exclusive access opcodes available in
the recent xtensa cores.
Since l32ex/s32ex don't have any memory ordering guarantees don't define
__smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/include/asm/barrier.h')
| -rw-r--r-- | arch/xtensa/include/asm/barrier.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/barrier.h b/arch/xtensa/include/asm/barrier.h index 956596e4d437..d6f8d4ddc2bc 100644 --- a/arch/xtensa/include/asm/barrier.h +++ b/arch/xtensa/include/asm/barrier.h @@ -9,12 +9,16 @@ #ifndef _XTENSA_SYSTEM_H #define _XTENSA_SYSTEM_H +#include <asm/core.h> + #define mb() ({ __asm__ __volatile__("memw" : : : "memory"); }) #define rmb() barrier() #define wmb() mb() +#if XCHAL_HAVE_S32C1I #define __smp_mb__before_atomic() barrier() #define __smp_mb__after_atomic() barrier() +#endif #include <asm-generic/barrier.h> |