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author | Fenghua Yu <fenghua.yu@intel.com> | 2014-05-29 22:12:30 +0400 |
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committer | H. Peter Anvin <hpa@linux.intel.com> | 2014-05-30 01:24:28 +0400 |
commit | 6229ad278ca74acdbc8bd3a3d469322a3de91039 (patch) | |
tree | d6e72f6129630ddbf3d46b9902fecf0fb331f364 /arch/x86/xen/spinlock.c | |
parent | 446fd806f5408b623fa51f3aa084e56844563779 (diff) | |
download | linux-6229ad278ca74acdbc8bd3a3d469322a3de91039.tar.xz |
x86/xsaves: Detect xsaves/xrstors feature
Detect the xsaveopt, xsavec, xgetbv, and xsaves features in processor extended
state enumberation sub-leaf (eax=0x0d, ecx=1):
Bit 00: XSAVEOPT is available
Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set
Bit 02: Supports XGETBV with ECX = 1 if set
Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set
The above features are defined in the new word 10 in cpu features.
The IA32_XSS MSR (index DA0H) contains a state-component bitmap that specifies
the state components that software has enabled xsaves and xrstors to manage.
If the bit corresponding to a state component is clear in XCR0 | IA32_XSS,
xsaves and xrstors will not operate on that state component, regardless of
the value of the instruction mask.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Link: http://lkml.kernel.org/r/1401387164-43416-3-git-send-email-fenghua.yu@intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/xen/spinlock.c')
0 files changed, 0 insertions, 0 deletions