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authorJani Nikula <jani.nikula@intel.com>2025-06-09 12:40:46 +0300
committerJani Nikula <jani.nikula@intel.com>2025-06-09 12:40:46 +0300
commit34c55367af96f62e89221444f04487440ebc6487 (patch)
treefdb36ba67d7dea09455b55037e26043b7e051ef9 /arch/x86/include/asm/microcode.h
parent7247efca0dcbc8ac6147db9200ed1549c0662465 (diff)
parent19272b37aa4f83ca52bdf9c16d5d81bdd1354494 (diff)
downloadlinux-34c55367af96f62e89221444f04487440ebc6487.tar.xz
Merge drm/drm-next into drm-intel-next
Sync to v6.16-rc1, among other things to get the fixed size GENMASK_U*() and BIT_U*() macros. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'arch/x86/include/asm/microcode.h')
-rw-r--r--arch/x86/include/asm/microcode.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 695e569159c1..8b41f26f003b 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -2,6 +2,8 @@
#ifndef _ASM_X86_MICROCODE_H
#define _ASM_X86_MICROCODE_H
+#include <asm/msr.h>
+
struct cpu_signature {
unsigned int sig;
unsigned int pf;
@@ -17,10 +19,12 @@ struct ucode_cpu_info {
void load_ucode_bsp(void);
void load_ucode_ap(void);
void microcode_bsp_resume(void);
+bool __init microcode_loader_disabled(void);
#else
static inline void load_ucode_bsp(void) { }
static inline void load_ucode_ap(void) { }
static inline void microcode_bsp_resume(void) { }
+static inline bool __init microcode_loader_disabled(void) { return false; }
#endif
extern unsigned long initrd_start_early;
@@ -61,7 +65,7 @@ static inline u32 intel_get_microcode_revision(void)
{
u32 rev, dummy;
- native_wrmsrl(MSR_IA32_UCODE_REV, 0);
+ native_wrmsrq(MSR_IA32_UCODE_REV, 0);
/* As documented in the SDM: Do a CPUID 1 here */
native_cpuid_eax(1);