summaryrefslogtreecommitdiff
path: root/arch/um/include/asm/pgalloc.h
diff options
context:
space:
mode:
authorBenjamin Berg <benjamin.berg@intel.com>2024-09-19 15:45:11 +0300
committerJohannes Berg <johannes.berg@intel.com>2024-10-10 14:37:22 +0300
commit41ab5fe7471ff38d2909d1c93b88197a89c6a00f (patch)
treeea76a3b75fd7d8d2b7a4be194e74081113d0b595 /arch/um/include/asm/pgalloc.h
parente167cc7a95fe01e228e403ac90090f8613e7d8bc (diff)
downloadlinux-41ab5fe7471ff38d2909d1c93b88197a89c6a00f.tar.xz
um: Switch to 4 level page tables on 64 bit
The larger memory space is useful to support more applications inside UML. One example for this is ASAN instrumentation of userspace applications which requires addresses that would otherwise not be available. Signed-off-by: Benjamin Berg <benjamin.berg@intel.com> Link: https://patch.msgid.link/20240919124511.282088-11-benjamin@sipsolutions.net Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Diffstat (limited to 'arch/um/include/asm/pgalloc.h')
-rw-r--r--arch/um/include/asm/pgalloc.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/um/include/asm/pgalloc.h b/arch/um/include/asm/pgalloc.h
index de5e31c64793..04fb4e6969a4 100644
--- a/arch/um/include/asm/pgalloc.h
+++ b/arch/um/include/asm/pgalloc.h
@@ -31,7 +31,7 @@ do { \
tlb_remove_page_ptdesc((tlb), (page_ptdesc(pte))); \
} while (0)
-#ifdef CONFIG_3_LEVEL_PGTABLES
+#if CONFIG_PGTABLE_LEVELS > 2
#define __pmd_free_tlb(tlb, pmd, address) \
do { \
@@ -39,6 +39,15 @@ do { \
tlb_remove_page_ptdesc((tlb), virt_to_ptdesc(pmd)); \
} while (0)
+#if CONFIG_PGTABLE_LEVELS > 3
+
+#define __pud_free_tlb(tlb, pud, address) \
+do { \
+ pagetable_pud_dtor(virt_to_ptdesc(pud)); \
+ tlb_remove_page_ptdesc((tlb), virt_to_ptdesc(pud)); \
+} while (0)
+
+#endif
#endif
#endif