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| author | Nicholas Piggin <npiggin@gmail.com> | 2020-11-26 13:25:27 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-11-26 16:10:39 +0300 |
| commit | 5844cc25fd121074de7895181a2fa1ce100a0fdd (patch) | |
| tree | 44e3ace7a4571f02e060faccd8eafdf52d797baf /arch/powerpc | |
| parent | b6b79dd53082db11070b4368d85dd6699ff0b063 (diff) | |
| download | linux-5844cc25fd121074de7895181a2fa1ce100a0fdd.tar.xz | |
powerpc/64s: Fix hash ISA v3.0 TLBIEL instruction generation
A typo has the R field of the instruction assigned by lucky dip a la
register allocator.
Fixes: d4748276ae14c ("powerpc/64s: Improve local TLB flush for boot and MCE on POWER9")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201126102530.691335-2-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/mm/book3s64/hash_native.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/mm/book3s64/hash_native.c b/arch/powerpc/mm/book3s64/hash_native.c index 0203cdf48c54..97fa42d7027e 100644 --- a/arch/powerpc/mm/book3s64/hash_native.c +++ b/arch/powerpc/mm/book3s64/hash_native.c @@ -68,7 +68,7 @@ static __always_inline void tlbiel_hash_set_isa300(unsigned int set, unsigned in rs = ((unsigned long)pid << PPC_BITLSHIFT(31)); asm volatile(PPC_TLBIEL(%0, %1, %2, %3, %4) - : : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "r"(r) + : : "r"(rb), "r"(rs), "i"(ric), "i"(prs), "i"(r) : "memory"); } |