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authorHaren Myneni <hbabu@us.ibm.com>2014-02-26 08:02:18 +0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-03-07 08:54:49 +0400
commit6b36ba8492abd1c819e949e085cc547b062d8593 (patch)
tree83f51a02cb13333cbd9675a135828e4316699107 /arch/powerpc/include/asm/rtas.h
parent39a33b59f43088aa33f29ace6b978333dd0bca4a (diff)
downloadlinux-6b36ba8492abd1c819e949e085cc547b062d8593.tar.xz
powerpc/pseries: Update dynamic cache nodes for suspend/resume operation
pHyp can change cache nodes for suspend/resume operation. Currently the device tree is updated by drmgr in userspace after all non boot CPUs are enabled. Hence, we do not modify the cache list based on the latest cache nodes. Also we do not remove cache entries for the primary CPU. This patch removes the cache list for the boot CPU, updates the device tree before enabling nonboot CPUs and adds cache list for the boot cpu. This patch also has the side effect that older versions of drmgr will perform a second device tree update from userspace. While this is a redundant waste of a couple cycles it is harmless since firmware returns the same data for the subsequent update-nodes/properties rtas calls. Signed-off-by: Haren Myneni <hbabu@us.ibm.com> Signed-off-by: Tyrel Datwyler <tyreld@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/rtas.h')
-rw-r--r--arch/powerpc/include/asm/rtas.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 9bd52c65e66f..a0e1add01ef5 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -283,6 +283,7 @@ extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
#ifdef CONFIG_PPC_PSERIES
extern int pseries_devicetree_update(s32 scope);
+extern void post_mobility_fixup(void);
#endif
#ifdef CONFIG_PPC_RTAS_DAEMON