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| author | Tony Lindgren <tony@atomide.com> | 2015-11-12 20:58:21 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2015-11-12 20:58:21 +0300 |
| commit | ff6d03b9d9cad592320ce21e9b22befe56ebe6b6 (patch) | |
| tree | da02d83177a107f92c446dbf7a93bdc1bac96cdf /arch/powerpc/boot/dts/fsl/p1020rdb.dts | |
| parent | 7ef71b70e18a82bb363905f72672317d0e1e8810 (diff) | |
| parent | 469689a45f78505d864210b3a5d75404eb7f24ee (diff) | |
| download | linux-ff6d03b9d9cad592320ce21e9b22befe56ebe6b6.tar.xz | |
Merge branch 'x15-audio-fixes' into omap-for-v4.4/fixes
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/p1020rdb.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/p1020rdb.dts | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p1020rdb.dts b/arch/powerpc/boot/dts/fsl/p1020rdb.dts new file mode 100644 index 000000000000..81362252bc8c --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/p1020rdb.dts @@ -0,0 +1,66 @@ +/* + * P1020 RDB Device Tree Source + * + * Copyright 2009-2011 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/include/ "p1020si-pre.dtsi" +/ { + model = "fsl,P1020RDB"; + compatible = "fsl,P1020RDB"; + + memory { + device_type = "memory"; + }; + + board_lbc: lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + + /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ + ranges = <0x0 0x0 0x0 0xef000000 0x01000000 + 0x1 0x0 0x0 0xffa00000 0x00040000 + 0x2 0x0 0x0 0xffb00000 0x00020000>; + }; + + board_soc: soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + }; + + pci0: pcie@ffe09000 { + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; + reg = <0 0xffe09000 0 0x1000>; + pcie@0 { + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + pci1: pcie@ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; + pcie@0 { + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; +}; + +/include/ "p1020rdb.dtsi" +/include/ "p1020si-post.dtsi" |