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| author | David S. Miller <davem@davemloft.net> | 2019-02-15 23:38:38 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-02-15 23:38:38 +0300 |
| commit | 3313da8188cc346a205783c22c37e821b4b7016d (patch) | |
| tree | 5697cd985220def9bc2e35dfbb832dad04c2d051 /arch/mips/boot/dts/xilfpga/nexys4ddr.dts | |
| parent | 50f444aa50a4f3fab35a04f56d6bb83dc1e8c875 (diff) | |
| parent | 24f0a48743a256bdec1bcb80708bc309da4aa261 (diff) | |
| download | linux-3313da8188cc346a205783c22c37e821b4b7016d.tar.xz | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
The netfilter conflicts were rather simple overlapping
changes.
However, the cls_tcindex.c stuff was a bit more complex.
On the 'net' side, Cong is fixing several races and memory
leaks. Whilst on the 'net-next' side we have Vlad adding
the rtnl-ness support.
What I've decided to do, in order to resolve this, is revert the
conversion over to using a workqueue that Cong did, bringing us back
to pure RCU. I did it this way because I believe that either Cong's
races don't apply with have Vlad did things, or Cong will have to
implement the race fix slightly differently.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/mips/boot/dts/xilfpga/nexys4ddr.dts')
| -rw-r--r-- | arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts index 2152b7ba65fb..cc8dbea0911f 100644 --- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts +++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts @@ -90,11 +90,11 @@ interrupts = <0>; }; - axi_i2c: i2c@10A00000 { + axi_i2c: i2c@10a00000 { compatible = "xlnx,xps-iic-2.00.a"; interrupt-parent = <&axi_intc>; interrupts = <4>; - reg = < 0x10A00000 0x10000 >; + reg = < 0x10a00000 0x10000 >; clocks = <&ext>; xlnx,clk-freq = <0x5f5e100>; xlnx,family = "Artix7"; @@ -106,9 +106,9 @@ #address-cells = <1>; #size-cells = <0>; - ad7420@4B { + ad7420@4b { compatible = "adi,adt7420"; - reg = <0x4B>; + reg = <0x4b>; }; } ; }; |