diff options
| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-06-20 18:26:42 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-06-27 11:44:24 +0300 |
| commit | a5c05453a13ab324ad8719e8a23dfb6af01f3652 (patch) | |
| tree | d18ef9dcf6d3c8789003228ee29a9a8813b2bfd9 /arch/mips/bcm63xx | |
| parent | 7c48090af524410fe72754be5f4cfd92d9487957 (diff) | |
| download | linux-a5c05453a13ab324ad8719e8a23dfb6af01f3652.tar.xz | |
mips: bmips: rework and cache CBR addr handling
Rework the handling of the CBR address and cache it. This address
doesn't change and can be cached instead of reading the register every
time.
This is in preparation of permitting to tweak the CBR address in DT with
broken SoC or bootloader.
bmips_cbr_addr is defined in setup.c for each arch to keep compatibility
with legacy brcm47xx/brcm63xx and generic BMIPS target.
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/bcm63xx')
| -rw-r--r-- | arch/mips/bcm63xx/prom.c | 3 | ||||
| -rw-r--r-- | arch/mips/bcm63xx/setup.c | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index c3a2ea62c5c3..f21dd168171a 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -22,6 +22,9 @@ void __init prom_init(void) { u32 reg, mask; + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); + bcm63xx_cpu_init(); /* stop any running watchdog */ diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index c13ddb544a23..16ea8945ae3a 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -12,6 +12,7 @@ #include <linux/memblock.h> #include <linux/ioport.h> #include <linux/pm.h> +#include <asm/bmips.h> #include <asm/bootinfo.h> #include <asm/time.h> #include <asm/reboot.h> @@ -22,6 +23,9 @@ #include <bcm63xx_io.h> #include <bcm63xx_gpio.h> +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; + void bcm63xx_machine_halt(void) { pr_info("System halted\n"); |