diff options
| author | Greg Ungerer <gerg@snapgear.com> | 2005-11-07 07:09:50 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-11-07 19:00:46 +0300 |
| commit | f15bf19b49854c984c27209bd4ade31a9c84f4de (patch) | |
| tree | f59e5b4fa5659749110800239e1f73cb9b8f35d2 /arch/m68knommu/platform | |
| parent | 88a605b02449852213a46f8a8ab760cfc5b9b7c8 (diff) | |
| download | linux-f15bf19b49854c984c27209bd4ade31a9c84f4de.tar.xz | |
[PATCH] m68knommu: modify the ColdFire PIT timer for new 5208
Modified common ColdFire PIT timer code to support the 5208 as well.
It uses a different set of mask and interrupt bits than other ColdFire
processors. The defines for these bits have been moved in header
files and set appropriately for the different processor varients.
Patch originally from Matt Waddel.
Signed-off-by: Greg Ungerer <gerg@uclinux.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/m68knommu/platform')
| -rw-r--r-- | arch/m68knommu/platform/5307/pit.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/m68knommu/platform/5307/pit.c b/arch/m68knommu/platform/5307/pit.c index a9b2c2e7e280..323f2677e49d 100644 --- a/arch/m68knommu/platform/5307/pit.c +++ b/arch/m68knommu/platform/5307/pit.c @@ -3,7 +3,7 @@ /* * pit.c -- Motorola ColdFire PIT timer. Currently this type of * hardware timer only exists in the Motorola ColdFire - * 5270/5271 and 5282 CPUs. + * 5270/5271, 5282 and other CPUs. * * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) @@ -47,10 +47,10 @@ void coldfire_pit_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)) icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + MCFINT_PIT1); - *icrp = 0x2b; /* PIT1 with level 5, priority 3 */ + *icrp = ICR_INTRCONF; - imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH); - *imrp &= ~(1 << (MCFINT_PIT1 - 32)); + imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR); + *imrp &= ~MCFPIT_IMR_IBIT; /* Set up PIT timer 1 as poll clock */ tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1); @@ -70,7 +70,7 @@ unsigned long coldfire_pit_offset(void) unsigned long pmr, pcntr, offset; tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1); - ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IPRH); + ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR); pmr = *(&tp->pmr); pcntr = *(&tp->pcntr); @@ -80,7 +80,7 @@ unsigned long coldfire_pit_offset(void) * timer interupt is pending, then add on a ticks worth of time. */ offset = ((pmr - pcntr) * (1000000 / HZ)) / pmr; - if ((offset < (1000000 / HZ / 2)) && (*ipr & (1 << (MCFINT_PIT1 - 32)))) + if ((offset < (1000000 / HZ / 2)) && (*ipr & MCFPIT_IMR_IBIT)) offset += 1000000 / HZ; return offset; } |