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| author | Gatien Chevallier <gatien.chevallier@foss.st.com> | 2025-09-01 12:16:29 +0300 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@foss.st.com> | 2025-09-15 18:51:31 +0300 |
| commit | bd0c7718ae1877e2e4eeb903096e905754d5df78 (patch) | |
| tree | 2e4231ce237ae22d1e5defecbb0e7f9bd8cc3b72 /arch/arm | |
| parent | 86803282a11801fb15360e52e6f2a7d7c7afdbec (diff) | |
| download | linux-bd0c7718ae1877e2e4eeb903096e905754d5df78.tar.xz | |
ARM: dts: stm32: add missing PTP reference clocks on stm32mp13x SoCs
ETH1/2 miss their PTP reference clock in the SoC device tree. Add them
as the fallback is not correctly handled for PPS generation and it seems
there's no reason to not add them.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20250901-relative_flex_pps-v4-3-b874971dfe85@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/st/stm32mp131.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/st/stm32mp133.dtsi | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 151ffd0bdef9..fd730aa37c22 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1609,11 +1609,13 @@ "mac-clk-tx", "mac-clk-rx", "ethstp", + "ptp_ref", "eth-ck"; clocks = <&rcc ETH1MAC>, <&rcc ETH1TX>, <&rcc ETH1RX>, <&rcc ETH1STP>, + <&rcc ETH1PTP_K>, <&rcc ETH1CK_K>; st,syscon = <&syscfg 0x4 0xff0000>; snps,mixed-burst; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 49583137b597..053fc6691205 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -81,11 +81,13 @@ "mac-clk-tx", "mac-clk-rx", "ethstp", + "ptp_ref", "eth-ck"; clocks = <&rcc ETH2MAC>, <&rcc ETH2TX>, <&rcc ETH2RX>, <&rcc ETH2STP>, + <&rcc ETH2PTP_K>, <&rcc ETH2CK_K>; st,syscon = <&syscfg 0x4 0xff000000>; snps,mixed-burst; |