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authorJoel Stanley <joel@jms.id.au>2020-07-24 05:30:35 +0300
committerJoel Stanley <joel@jms.id.au>2020-07-24 08:19:03 +0300
commitb23b2b842002424147b820f22d52a8306bd7b2ac (patch)
treeae76631e271c90df76d603ca4611a337efaf2c4e /arch/arm
parent0ce0581e6d32040696effd1b2298618c3aa3a595 (diff)
downloadlinux-b23b2b842002424147b820f22d52a8306bd7b2ac.tar.xz
ARM: dts: aspeed: rainier: Add CFAM reset GPIO
The GPIO on Q0 is used for resetting the CFAM of the processor that the ASPEED master is connected to. The signal is wired as active high on the first pass systems. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
index ac7cc96a15d3..e91f3bc7a0c2 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
@@ -125,6 +125,12 @@
#address-cells = <2>;
#size-cells = <0>;
+ /*
+ * CFAM Reset is supposed to be active low but pass1 hardware is wired
+ * active high.
+ */
+ cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
+
cfam@0,0 {
reg = <0 0>;
#address-cells = <1>;