diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2021-01-21 13:26:53 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-02-01 12:36:26 +0300 |
| commit | 51733f16c6419df8b2cb4c254d249eae1e03d6c8 (patch) | |
| tree | eb09051447f142bfa428c8acda842bf0adb5a780 /arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | |
| parent | 42cb66dcd5f7c40e31adc162122f6428021f97e5 (diff) | |
| download | linux-51733f16c6419df8b2cb4c254d249eae1e03d6c8.tar.xz | |
arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
Enable psgtr driver and write clocks property to get sata to work.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/80b52ef97501968ee97fc152363bc4b9b7bb2cff.1611224800.git.michal.simek@xilinx.com
Diffstat (limited to 'arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 7a4614e3f5fa..5e2be9abc175 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -12,6 +12,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> / { model = "ZynqMP ZCU104 RevA"; @@ -36,6 +37,24 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + clock_8t49n287_5: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clock_8t49n287_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_8t49n287_3: clk27 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; }; &can1 { @@ -158,6 +177,13 @@ status = "okay"; }; +&psgtr { + status = "okay"; + /* nc, sata, usb3, dp */ + clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; + clock-names = "ref1", "ref2", "ref3"; +}; + &sata { status = "okay"; /* SATA OOB timing settings */ @@ -169,6 +195,8 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ |