diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-04-05 09:34:44 +0300 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-04-12 17:21:15 +0300 |
| commit | 2374b99e19ac7f2beca2d4e62ebb96803db0e66b (patch) | |
| tree | f99261f0c6ad71d3a2aaf633df084feb175a7555 /arch/arm64/boot/dts/qcom/msm8994.dtsi | |
| parent | 0e1b27f4f69e86b8b62ba5bedb78936341433247 (diff) | |
| download | linux-2374b99e19ac7f2beca2d4e62ebb96803db0e66b.tar.xz | |
arm64: dts: qcom: align clocks in I2C/SPI with DT schema
The DT schema expects clocks core-iface order. No functional change.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8994.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8994.dtsi | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 8c1dc5155b71..209f9ef030e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -519,9 +519,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9923000 0x500>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dma-names = "tx", "rx"; @@ -555,9 +555,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; dma-names = "tx", "rx"; @@ -575,9 +575,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9926000 0x500>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; dma-names = "tx", "rx"; @@ -593,9 +593,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9927000 0x500>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dma-names = "tx", "rx"; @@ -611,9 +611,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9928000 0x500>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; dma-names = "tx", "rx"; @@ -657,9 +657,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9963000 0x500>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; dma-names = "tx", "rx"; @@ -693,9 +693,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9967000 0x500>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <355000>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dma-names = "tx", "rx"; |