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authorKathiravan T <quic_kathirav@quicinc.com>2022-02-08 18:35:25 +0300
committerBjorn Andersson <bjorn.andersson@linaro.org>2022-02-11 03:12:05 +0300
commit3d44861d006b18649306cbade242c865e9068b6e (patch)
tree9e88e0c5e13f526a995ff66f5edd57596893f8fb /arch/arm64/boot/dts/qcom/ipq6018.dtsi
parent59892de947f0ca1d65426f7a6c6e258863fa65d7 (diff)
downloadlinux-3d44861d006b18649306cbade242c865e9068b6e.tar.xz
arm64: dts: qcom: ipq6018: enable the GICv2m support
GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension, which supports upto 32 MSI interrupts. Lets add support for the same. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@quicinc.com
Diffstat (limited to 'arch/arm64/boot/dts/qcom/ipq6018.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/ipq6018.dtsi9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index aa8068193ccb..f8b6d6263c61 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -373,6 +373,8 @@
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
+ #address-cells = <2>;
+ #size-cells = <2>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
@@ -380,6 +382,13 @@
<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ ranges = <0 0 0 0xb00a000 0 0xffd>;
+
+ v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x0 0x0 0x0 0xffd>;
+ };
};
pcie_phy: phy@84000 {