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| author | Yunfei Dong <yunfei.dong@mediatek.com> | 2023-12-20 16:33:02 +0300 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-02-12 15:37:02 +0300 |
| commit | 7f62dae2e91f950415d0a7f24484f34e85dd9c6c (patch) | |
| tree | 753ae88a57a7fcb31ca43899d525e4f134f00eda /arch/arm64/boot/dts/mediatek/mt8186.dtsi | |
| parent | 795d5f0c8468fb5c20886347d9fe3575f1f21086 (diff) | |
| download | linux-7f62dae2e91f950415d0a7f24484f34e85dd9c6c.tar.xz | |
arm64: dts: mediatek: mt8186: Add video decoder device nodes
Add mt8186 video decoder device nodes.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
[eugen.hristev@collabora.com: minor cleanup]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Link: https://lore.kernel.org/r/20231220133302.39411-1-eugen.hristev@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8186.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8186.dtsi | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index adaf5e57fac5..8f18b0fd690c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1963,6 +1963,43 @@ power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; }; + video_decoder: video-decoder@16000000 { + compatible = "mediatek,mt8186-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>; + mediatek,scp = <&scp>; + + vcodec_core: video-codec@16025000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x16025000 0 0x1000>; + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&iommu_mm IOMMU_PORT_L4_HW_VDEC_MC_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PP_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_TILE_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_VLD2_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT>, + <&iommu_mm IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>, + <&topckgen CLK_TOP_UNIVPLL_D3>; + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec", "vdec-top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>; + power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; + }; + }; + larb4: smi@1602e000 { compatible = "mediatek,mt8186-smi-larb"; reg = <0 0x1602e000 0 0x1000>; |