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| author | Andrew Lunn <andrew@lunn.ch> | 2023-04-07 18:18:39 +0300 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2023-04-07 18:41:05 +0300 |
| commit | 218669c662e3a38fdbd7e0ce56a20784da29546e (patch) | |
| tree | 865249c6e96d212d823f929b6ae1e9a0f47583c1 /arch/arm64/boot/dts/marvell | |
| parent | 6d5a6740f6df4c41a96d57d542207a7d5cab0393 (diff) | |
| download | linux-218669c662e3a38fdbd7e0ce56a20784da29546e.tar.xz | |
ARM64: dts: marvell: cn9310: Add missing phy-mode
The DSA framework has got more picky about always having a phy-mode
for the CPU port. The SoC Ethernet is being configured to
10gbase-r. Set the switch phy-mode based on this. Additionally, the
SoC Ethernet is using in-band signalling to determine the link speed,
so add same parameter to the switch.
Additionally, the cpu label has never actually been used in the
binding, so remove it.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 8e4ec243fb8f..32cfb3e2efc3 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -282,8 +282,9 @@ port@a { reg = <10>; - label = "cpu"; ethernet = <&cp0_eth0>; + phy-mode = "10gbase-r"; + managed = "in-band-status"; }; }; |