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| author | Stephen Warren <swarren@nvidia.com> | 2019-10-03 23:50:33 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-01-08 14:58:46 +0300 |
| commit | 9c65b8463f41f3a9edef97e3109752159d4c6a4b (patch) | |
| tree | 6ef4689fff868dbe8db624ddf99d99ff5d6cbb5c /arch/arm/mach-tegra | |
| parent | cf94a7a06a7d7d4402d7313cf622ca2823bad43c (diff) | |
| download | linux-9c65b8463f41f3a9edef97e3109752159d4c6a4b.tar.xz | |
ARM: tegra: Use clk_m CPU on Tegra124 LP1 resume
Configure the clock controller to set an alternate clock for the CPU
when it receives an IRQ during LP1 (system suspend). Specifically, use
clk_m (the crystal) rather than clk_s (a 32KHz clock). Such an IRQ will
be the LP1 wake event. This reduces the amount of time taken to resume
from LP1.
NVIDIA's downstream kernel executes this code on both Tegra30 and
Tegra124, so it appears OK to make this change unconditionally.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-tegra30.S | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index f01ea3be1405..02cc6ff96f30 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -670,8 +670,12 @@ tegra30_switch_cpu_to_clk32k: pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ _no_pll_in_iddq: - /* switch to CLKS */ - mov r0, #0 /* brust policy = 32KHz */ + /* + * Switch to clk_s (32KHz); bits 28:31=0 + * Enable burst on CPU IRQ; bit 24=1 + * Set IRQ burst clock source to clk_m; bits 10:8=0 + */ + mov r0, #(1 << 24) str r0, [r5, #CLK_RESET_SCLK_BURST] ret lr |