diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2022-09-29 16:26:06 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-01-12 12:53:12 +0300 |
| commit | 9a9e1be12c6d49e15429311714c4b1cc4ddcfe55 (patch) | |
| tree | 2c3f33f78a1d3661c5eff52e9a65018117cdd4fc /arch/arm/mach-sa1100/include/mach/nanoengine.h | |
| parent | 8faf91c48ca20c714e0dd8cc5f510e3819852912 (diff) | |
| download | linux-9a9e1be12c6d49e15429311714c4b1cc4ddcfe55.tar.xz | |
ARM: sa1100: remove unused board files
The Cerf, H3100, Badge4, Hackkit, LART, NanoEngine, PLEB, Shannon and
Simpad machines were all marked as unused as there are no known users
left. Remove all of these, along with references to them in defconfig
files and drivers.
Four machines remain now: Assabet, Collie (Zaurus SL5500), iPAQ H3600
and Jornada 720, each of which had one person still using them, with
Collie also being supported in Qemu.
Cc: Peter Chubb <peter.chubb@unsw.edu.au>
Cc: Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-sa1100/include/mach/nanoengine.h')
| -rw-r--r-- | arch/arm/mach-sa1100/include/mach/nanoengine.h | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h deleted file mode 100644 index 8d5ee1438956..000000000000 --- a/arch/arm/mach-sa1100/include/mach/nanoengine.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-sa1100/include/mach/nanoengine.h - * - * This file contains the hardware specific definitions for nanoEngine. - * Only include this file from SA1100-specific files. - * - * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> - */ -#ifndef __ASM_ARCH_NANOENGINE_H -#define __ASM_ARCH_NANOENGINE_H - -#include <mach/irqs.h> - -#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/ -#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ -#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ -#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ -#define GPIO_PC_RESET0 15 /* reset socket 0 */ -#define GPIO_PC_RESET1 16 /* reset socket 1 */ - -#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 -#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 -#define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12 -#define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13 -#define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14 - -/* - * nanoEngine Memory Map: - * - * 0000.0000 - 003F.0000 - 4 MB Flash - * C000.0000 - C1FF.FFFF - 32 MB SDRAM - * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write - * 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space - * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode - * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode - * - */ - -#define NANO_PCI_MEM_RW_PHYS 0x18600000 -#define NANO_PCI_MEM_RW_VIRT 0xf1000000 -#define NANO_PCI_MEM_RW_SIZE SZ_1M -#define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000 -#define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000 -#define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K - -#endif - |