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authorChen-Yu Tsai <wens@csie.org>2017-06-06 08:59:31 +0300
committerChen-Yu Tsai <wens@csie.org>2017-08-05 17:06:58 +0300
commit23ee53b1e262dcb19901f15a53428ead6a2bf137 (patch)
tree993d39746510acc0075523786b416f29359d904c /arch/arm/boot/dts/sun8i-a83t.dtsi
parenta180791004fa28b2727a01df114941cbbf2a06d5 (diff)
downloadlinux-23ee53b1e262dcb19901f15a53428ead6a2bf137.tar.xz
ARM: dts: sun8i: a83t: Add device node for R_INTC interrupt controller
The R_INTC interrupt controller handles the NMI interrupt pin for the SoC. While there is no documentation or code from the vendor for this device on the A83T, existing mainline kernel drivers and bindings show this to be similar to the old Allwinner interrupt controller found on the A10 SoC, but with only the NMI interrupt wired. Register poking experiments confirm this. The device seems to be the same across all recent Allwinner SoCs, apart from the A20 and A80, which have a separate set of registers to handle the NMI interrupt. We already have a set of bindings supporting this on the A31. Add a device node for it, with an SoC specific compatible. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a83t.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-a83t.dtsi9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 19a8f4fcfab5..beed05e10a3b 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -281,6 +281,15 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ r_intc: interrupt-controller@1f00c00 {
+ compatible = "allwinner,sun8i-a83t-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c00 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-a83t-r-ccu";
reg = <0x01f01400 0x400>;