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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2017-07-29 00:13:13 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2017-08-01 22:33:47 +0300 |
| commit | 45631ea8b5d814845a9e3a246ea79c89d63bf786 (patch) | |
| tree | 54dfa8af3a9ed8ee1882f2040942626074ba2404 /arch/arm/boot/dts/meson8.dtsi | |
| parent | 40b5c4f30c7f93c63836521d5be4e66eeb864539 (diff) | |
| download | linux-45631ea8b5d814845a9e3a246ea79c89d63bf786.tar.xz | |
ARM: dts: meson: mark the clock controller also as reset controller
The clock controller provides a few reset lines as well. Add the
corresponding CPU cores.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 6fe6a159e960..b98d44fde6b6 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -168,6 +168,7 @@ &cbus { clkc: clock-controller@4000 { #clock-cells = <1>; + #reset-cells = <1>; compatible = "amlogic,meson8-clkc"; reg = <0x8000 0x4>, <0x4000 0x460>; }; |