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authorLinus Walleij <linus.walleij@linaro.org>2021-07-16 02:58:54 +0300
committerLinus Walleij <linus.walleij@linaro.org>2021-08-09 02:55:10 +0300
commitf2791ed73193f0f0a5b5fa41da1ee4dfefa64a68 (patch)
treedfc30ea167d7db9516b1192a5ac884d4467690e4 /arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
parente647167967f84b95f64c9ff14dc161fbd645e5cc (diff)
downloadlinux-f2791ed73193f0f0a5b5fa41da1ee4dfefa64a68.tar.xz
ARM: dts: ixp4xx: Use the expansion bus
Replace the "simple-bus" simplification by the proper bus for IXP4xx memory or device expansion. Use chip-select addressing with two address cells on all the flashes mounted on the IXP4xx devices. This includes all flash chips. Change the unit-name from @50000000 to @c4000000 as the DTS validation screams. The registers for controlling the bus are at c4000000 but the actual memory windows and ranges are at 50000000. Well it is just syntax, we can live with it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts')
-rw-r--r--arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
index 4ea8be3449f9..8b32e9f22d81 100644
--- a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts
@@ -99,16 +99,16 @@
};
soc {
- bus@50000000 {
+ bus@c4000000 {
/* The first 16MB region at CS0 on the expansion bus */
- flash@0 {
+ flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/*
* 16 MB of Flash in 128 0x20000 sized blocks
* mapped in at CS0.
*/
- reg = <0x00000000 0x1000000>;
+ reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";