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authorFabio Estevam <fabio.estevam@freescale.com>2015-06-26 20:10:53 +0300
committerShawn Guo <shawnguo@kernel.org>2015-08-11 18:15:10 +0300
commitd28be499c45e6e16d7a042ce280eb872dc06952b (patch)
tree133e4665ba160462a5c313776e3e027794848dca /arch/arm/boot/dts/imx6qdl-sabresd.dtsi
parentfb00ff4c30a8cce32371e5d1abcbb33be1b6d506 (diff)
downloadlinux-d28be499c45e6e16d7a042ce280eb872dc06952b.tar.xz
ARM: dts: imx6qdl-sabresd: Allow HDMI and LVDS to work simultaneously
Currently it is not possible to have HDMI and LVDS working simultaneously, because both ports try to use PLL5. Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be driven from independent sources. With this change the LDB pixel clock goes to 68.57 MHz, which is still within the valid range for the HSD100PXN1 LVDS panel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabresd.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index a626e6dd8022..cca847e448a0 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -141,6 +141,13 @@
status = "okay";
};
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 9 0>;