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authorAlexander Shiyan <shc_work@mail.ru>2014-04-26 08:52:07 +0400
committerShawn Guo <shawn.guo@freescale.com>2014-05-16 19:02:03 +0400
commit198e31d08bd3caeb58c54232f1a06a9097715158 (patch)
treec578d5bd8d54d250d24b694055ab7e65f44bb675 /arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
parent560723a54965155be9360ea031956082e947184d (diff)
downloadlinux-198e31d08bd3caeb58c54232f1a06a9097715158.tar.xz
ARM: dts: imx27-phytec-phycore-som: Fix active level for FEC reset
FEC reset GPIO is active low. Fix this typo. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi')
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index 32cc7dac9ab6..93482e9d2c93 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -182,7 +182,7 @@
&fec {
phy-mode = "mii";
- phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+ phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;