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authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>2013-07-26 17:17:57 +0400
committerJason Cooper <jason@lakedaemon.net>2013-08-06 18:11:16 +0400
commit5e12a613ce393472316063dab062ad1afad84cc5 (patch)
treee1eb06eebbd8f9c75851413d2f811b11bf28f0b0 /arch/arm/boot/dts/armada-370-xp.dtsi
parent38149887ef8bfdc3d95e84a5b0a344241787d2d7 (diff)
downloadlinux-5e12a613ce393472316063dab062ad1afad84cc5.tar.xz
ARM: mvebu: Add MBus to Armada 370/XP device tree
The Armada 370/XP SoC family has a completely configurable address space handled by the MBus controller. This patch introduces the device tree layout of MBus, making the 'soc' node as mbus-compatible. Since every peripheral/controller is a child of this 'soc' node, this makes all of them sit behind the mbus, thus describing the hardware accurately. A translation entry has been added for the internal-regs mapping. This can't be done in the common armada-370-xp.dtsi because A370 and AXP have different addressing width. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-370-xp.dtsi')
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi15
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90b117624abb..62639b4a61f9 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -18,6 +18,8 @@
/include/ "skeleton64.dtsi"
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
/ {
model = "Marvell Armada 370 and XP SoC";
compatible = "marvell,armada-370-xp";
@@ -38,18 +40,21 @@
};
soc {
- #address-cells = <1>;
+ #address-cells = <2>;
#size-cells = <1>;
- compatible = "simple-bus";
+ controller = <&mbusc>;
interrupt-parent = <&mpic>;
- ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+ mbusc: mbus-controller@20000 {
+ compatible = "marvell,mbus-controller";
+ reg = <0x20000 0x100>, <0x20180 0x20>;
+ };
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";