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| author | Jim Quinlan <jim2101024@gmail.com> | 2022-01-06 19:03:26 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-12 22:45:50 +0300 |
| commit | ea372f45cfff7774c57f685b0c1a86951a15e18a (patch) | |
| tree | 775fbe8f9b788c5efd97788977495c31e5de8928 /Documentation | |
| parent | 504253e44a9dc91e535f84273ebded324de4d2f6 (diff) | |
| download | linux-ea372f45cfff7774c57f685b0c1a86951a15e18a.tar.xz | |
dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
Add bindings for Brcmstb EP voltage regulators. A new mechanism is to be
added to the Linux PCI subsystem that will allocate and turn on/off
regulators. These are standard regulators -- vpcie12v, vpcie3v3, and
vpcie3v3aux -- placed in the DT in the bridge node under the host bridge
device.
The use of a regulator property in the PCIe EP subnode such as
"vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
file at
https://github.com/devicetree-org/dt-schema/pull/63
Link: https://lore.kernel.org/r/20220106160332.2143-4-jim2101024@gmail.com
Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 22f2ef446f18..3e3c8929c97c 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -159,5 +159,24 @@ examples: <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; brcm,enable-ssc; brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; + + /* PCIe bridge, Root Port */ + pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + vpcie3v3-supply = <&vreg7>; + ranges; + + /* PCIe endpoint */ + pci-ep@0,0 { + assigned-addresses = + <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pci14e4,1688"; + }; + }; }; }; |