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authorJakub Kicinski <kuba@kernel.org>2026-04-12 18:27:43 +0300
committerJakub Kicinski <kuba@kernel.org>2026-04-12 18:27:44 +0300
commitd24b443429e071e4dad662c440e2ea56000accba (patch)
tree061c0104315caa2d1a03f4a4ce49971cea9a621e /Documentation
parent3f3a2aefbc661b837c8e344f944982d61c2ae037 (diff)
parent14f269ae699869ddaca7c29c9c6c52288e3bfb73 (diff)
downloadlinux-d24b443429e071e4dad662c440e2ea56000accba.tar.xz
Merge branch 'dpll-zl3073x-add-ref-sync-pair-support'
Ivan Vecera says: ==================== dpll: zl3073x: add ref-sync pair support This series adds Reference-Sync pair support to the ZL3073x DPLL driver. A Ref-Sync pair consists of a clock reference and a low-frequency sync signal (e.g. 1 PPS) where the DPLL locks to the clock reference but phase-aligns to the sync reference. Patches 1-3 are preparatory cleanups and helper additions: - Clean up esync get/set callbacks with early returns and use the zl3073x_out_is_ndiv() helper - Convert open-coded clear-and-set bitfield patterns to FIELD_MODIFY() - Add ref sync control and output clock type accessor helpers Patch 4 adds the 'ref-sync-sources' phandle-array property to the dpll-pin device tree binding schema and updates the ZL3073x binding examples. Patch 5 implements the driver support: - ref_sync_get/set callbacks with frequency validation - Automatic sync source exclusion from reference selection - Device tree based ref-sync pair registration Tested and verified on Microchip EDS2 (pcb8385) development board. ==================== Link: https://patch.msgid.link/20260408102716.443099-1-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/dpll/dpll-pin.yaml13
-rw-r--r--Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml30
2 files changed, 36 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml
index 51db93b77306..1287a472f08f 100644
--- a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml
+++ b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml
@@ -36,6 +36,19 @@ properties:
description: String exposed as the pin board label
$ref: /schemas/types.yaml#/definitions/string
+ ref-sync-sources:
+ description: |
+ List of phandles to input pins that can serve as the sync source
+ in a Reference-Sync pair with this pin acting as the clock source.
+ A Ref-Sync pair consists of a clock reference and a low-frequency
+ sync signal. The DPLL locks to the clock reference but
+ phase-aligns to the sync reference.
+ Only valid for input pins. Each referenced pin must be a
+ different input pin on the same device.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 1
+
supported-frequencies-hz:
description: List of supported frequencies for this pin, expressed in Hz.
diff --git a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
index 17747f754b84..fa5a8f8e390c 100644
--- a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
+++ b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
@@ -52,11 +52,19 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
- pin@0 { /* REF0P */
+ sync0: pin@0 { /* REF0P - 1 PPS sync source */
reg = <0>;
connection-type = "ext";
- label = "Input 0";
- supported-frequencies-hz = /bits/ 64 <1 1000>;
+ label = "SMA1";
+ supported-frequencies-hz = /bits/ 64 <1>;
+ };
+
+ pin@1 { /* REF0N - clock source, can pair with sync0 */
+ reg = <1>;
+ connection-type = "ext";
+ label = "SMA2";
+ supported-frequencies-hz = /bits/ 64 <10000 10000000>;
+ ref-sync-sources = <&sync0>;
};
};
@@ -90,11 +98,19 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
- pin@0 { /* REF0P */
+ sync1: pin@0 { /* REF0P - 1 PPS sync source */
reg = <0>;
- connection-type = "ext";
- label = "Input 0";
- supported-frequencies-hz = /bits/ 64 <1 1000>;
+ connection-type = "gnss";
+ label = "GNSS_1PPS_IN";
+ supported-frequencies-hz = /bits/ 64 <1>;
+ };
+
+ pin@1 { /* REF0N - clock source */
+ reg = <1>;
+ connection-type = "gnss";
+ label = "GNSS_10M_IN";
+ supported-frequencies-hz = /bits/ 64 <10000000>;
+ ref-sync-sources = <&sync1>;
};
};