Merge tag 'gpio-updates-for-v6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

Pull gpio updates from Bartosz Golaszewski:
 "Thanks to little activity in December, this is really tiny. Just a few
  updates to drivers and device-tree bindings.

  Driver improvements:
   - support a new model in gpio-mpc8xxx
   - refactor gpio-tqmx86 and add support for direction setting
   - allow building gpio-omap with COMPILE_TEST=y
   - use gpiochip_get_data() instead of dev_get_drvdata() in
     gpio-twl6040
   - drop unued field from driver data in gpio-altera
   - use generic request/free callbacks in gpio-regmap for better
     integration with pinctrl
   - use dev_err_probe() where applicable in gpio-pca953x
   - use existing dedicated GPIO defines in gpio-tps65219 instead of
     custom ones

  DT bindings:
   - document a new model in fsl,qoriq-gpio
   - explain the chip's latch clock pin and how it works like
     chip-select in fairchild,74hc595
   - enable the gpio-line-names property for gpio-brcmstb"

* tag 'gpio-updates-for-v6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux:
  gpio: regmap: Use generic request/free ops
  gpio: altera: Drop .mapped_irq from driver data
  gpio: mpc8xxx: Add MPC8314 support
  dt-bindings: gpio: fsl,qoriq-gpio: Add compatible string fsl,mpc8314-gpio
  dt-bindings: gpio: fairchild,74hc595: Document chip select vs. latch clock
  gpio: tps65219: Use existing kernel gpio macros
  gpio: pca953x: log an error when failing to get the reset GPIO
  dt-bindings: gpio: brcmstb: permit gpio-line-names property
  gpio: tqmx86: add support for changing GPIO directions
  gpio: tqmx86: introduce tqmx86_gpio_clrsetbits() helper
  gpio: tqmx86: use cleanup guards for spinlock
  gpio: tqmx86: consistently refer to IRQs by hwirq numbers
  gpio: tqmx86: add macros for interrupt configuration
  gpio: omap: allow building the module with COMPILE_TEST=y
  gpio: twl4030: use gpiochip_get_data

3 files changed, 22 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
index f096f286da19..fbd69b4cecc7 100644
--- a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
@@ -64,6 +64,10 @@ properties:
 
   gpio-ranges: true
 
+  gpio-line-names:
+    minItems: 1
+    maxItems: 128
+
   wakeup-source:
     type: boolean
     description: >
diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
index e8bc9f018edb..0e5c22929bde 100644
--- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
+++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
@@ -6,6 +6,23 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Generic 8-bit shift register
 
+description: |
+  NOTE: These chips nominally don't have a chip select pin. They do however
+  have a rising-edge triggered latch clock (or storage register clock) pin,
+  which behaves like an active-low chip select.
+
+  After the bits are shifted into the shift register, CS# is driven high, which
+  the 74HC595 sees as a rising edge on the latch clock that results in a
+  transfer of the bits from the shift register to the storage register and thus
+  to the output pins.
+                      _   _       _   _
+  shift clock    ____| |_| |_..._| |_| |_________
+
+  latch clock                           * trigger
+                 ___                     ________
+  chip select#      |___________________|
+
+
 maintainers:
   - Maxime Ripard <mripard@kernel.org>
 
diff --git a/Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml b/Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml
index 84fd82291ee4..f1b60ab3f356 100644
--- a/Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/fsl,qoriq-gpio.yaml
@@ -15,6 +15,7 @@ properties:
       - enum:
           - fsl,mpc5121-gpio
           - fsl,mpc5125-gpio
+          - fsl,mpc8314-gpio
           - fsl,mpc8349-gpio
           - fsl,mpc8572-gpio
           - fsl,mpc8610-gpio