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authorDave Jiang <dave.jiang@intel.com>2025-11-13 18:47:49 +0300
committerDave Jiang <dave.jiang@intel.com>2025-11-13 18:47:49 +0300
commit482dc84e91a597149949f18c8eefb49cb2dc1bee (patch)
tree97ecf30058bc7159c333f68875288558db50e59b /Documentation
parent87c69670daba100809144e637bc29335c48231cc (diff)
parentd6602e25819dea2c239972e98e09ba5db4aebd22 (diff)
downloadlinux-482dc84e91a597149949f18c8eefb49cb2dc1bee.tar.xz
Merge branch 'for-6.19/cxl-elc' into cxl-for-next
- Add extended linear cache size sysfs attribute. - Adjust failure emission of extended linear cache detection in cxl_acpi.
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/ABI/testing/sysfs-bus-cxl11
1 files changed, 10 insertions, 1 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
index 6b4e8c7a963d..c80a1b5a03db 100644
--- a/Documentation/ABI/testing/sysfs-bus-cxl
+++ b/Documentation/ABI/testing/sysfs-bus-cxl
@@ -496,8 +496,17 @@ Description:
changed, only freed by writing 0. The kernel makes no guarantees
that data is maintained over an address space freeing event, and
there is no guarantee that a free followed by an allocate
- results in the same address being allocated.
+ results in the same address being allocated. If extended linear
+ cache is present, the size indicates extended linear cache size
+ plus the CXL region size.
+What: /sys/bus/cxl/devices/regionZ/extended_linear_cache_size
+Date: October, 2025
+KernelVersion: v6.19
+Contact: linux-cxl@vger.kernel.org
+Description:
+ (RO) The size of extended linear cache, if there is an extended
+ linear cache. Otherwise the attribute will not be visible.
What: /sys/bus/cxl/devices/regionZ/mode
Date: January, 2023