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authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2021-11-15 20:11:17 +0300
committerJakub Kicinski <kuba@kernel.org>2021-11-17 06:22:30 +0300
commitb9241f54138ca5af4d3c5ca6db56be83d7491508 (patch)
tree20b311f2f7145d0f2406a7b49bd3c3315ea39c6e /Documentation/networking/phy.rst
parentbe0f6c4100acc38129c9578ddc11b6a9dd7fb4ef (diff)
downloadlinux-b9241f54138ca5af4d3c5ca6db56be83d7491508.tar.xz
net: document SMII and correct phylink's new validation mechanism
SMII has not been documented in the kernel, but information on this PHY interface mode has been recently found. Document it, and correct the recently introduced phylink handling for this interface mode. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/E1mmfVl-0075nP-14@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@@ -237,6 +237,11 @@ negotiation results.
Some of the interface modes are described below:
+``PHY_INTERFACE_MODE_SMII``
+ This is serial MII, clocked at 125MHz, supporting 100M and 10M speeds.
+ Some details can be found in
+ https://opencores.org/ocsvn/smii/smii/trunk/doc/SMII.pdf
+
``PHY_INTERFACE_MODE_1000BASEX``
This defines the 1000BASE-X single-lane serdes link as defined by the
802.3 standard section 36. The link operates at a fixed bit rate of