Merge tag 'edac_for_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

Pull EDAC updates from Borislav Petkov:

 - Support for ZynqMP DDR controller support to synopsys_edac along with
   a driver cleanup and generalization for the addition of support for
   the new IP. (Manish Narani)

 - Removal of the /sys/bus/edac devices hierarchy. This enabled us to
   get rid of the silly memory controllers maximum number notion. (Tony
   Luck and Borislav Petkov)

 - skx_edac improvements and fixes. (Qiuxu Zhuo and Tony Luck)

 - The usual garden variety of small cleanups and fixes.

* tag 'edac_for_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (25 commits)
  EDAC, fsl_ddr: Add LS1021A to the list of supported hardware
  EDAC, i5000: Remove set but not used local variables
  MAINTAINERS, EDAC: Drop bouncing email
  EDAC, i82975x: Fix spelling mistake "reserverd" -> "reserved"
  EDAC, fsl: Move error injection under CONFIG_EDAC_DEBUG
  EDAC, skx: Let EDAC core show the decoded result for debugfs
  EDAC, skx: Move debugfs node under EDAC's hierarchy
  EDAC, skx: Prepend hex formatting with '0x'
  EDAC, skx: Fix function calling order in skx_exit()
  EDAC: Drop per-memory controller buses
  EDAC: Don't add devices under /sys/bus/edac
  EDAC: Fix indentation issues in several EDAC drivers
  EDAC, skx: Fix randconfig builds in a better way
  EDAC, i82975x: Remove set but not used variable dtype
  EDAC, qcom_edac: Remove irq_handled local variable
  EDAC, synopsys: Add Error Injection support for ZynqMP DDR controller
  EDAC, synopsys: Add ECC support for ZynqMP DDR controller
  EDAC, synopsys: Add macro defines for ZynqMP DDRC
  dt: bindings: Document ZynqMP DDRC in Synopsys documentation
  EDAC, synopsys: Add error handling for the of_device_get_match_data() result
  ...

1 files changed, 22 insertions, 5 deletions

diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
index a43d26d41e04..9d32762c47e1 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -1,15 +1,32 @@
 Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
 
-This controller has an optional ECC support in half-bus width (16-bit)
-configuration. The ECC controller corrects one bit error and detects
-two bit errors.
+The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
+bus width configurations.
+
+The Zynq DDR ECC controller has an optional ECC support in half-bus width
+(16-bit) configuration.
+
+These both ECC controllers correct single bit ECC errors and detect double bit
+ECC errors.
 
 Required properties:
- - compatible: Should be 'xlnx,zynq-ddrc-a05'
- - reg: Base address and size of the controllers memory area
+ - compatible: One of:
+	- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
+	- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
+ - reg: Should contain DDR controller registers location and length.
+
+Required properties for "xlnx,zynqmp-ddrc-2.40a":
+ - interrupts: Property with a value describing the interrupt number.
 
 Example:
 	memory-controller@f8006000 {
 		compatible = "xlnx,zynq-ddrc-a05";
 		reg = <0xf8006000 0x1000>;
 	};
+
+	mc: memory-controller@fd070000 {
+		compatible = "xlnx,zynqmp-ddrc-2.40a";
+		reg = <0x0 0xfd070000 0x0 0x30000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 112 4>;
+	};