diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-07-18 04:07:31 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-07-18 04:07:31 +0300 |
| commit | 0ffb8a4c96e55ecf0e572aec1a0220af3da84e22 (patch) | |
| tree | ea497c6728d2b93b31f1f4535a1413a436a59683 /Documentation/devicetree | |
| parent | 5b9ac6c2a735f5b1721e0bc7331f8707190f9ef6 (diff) | |
| parent | 76be2f9823b10c07daf814cb6c732eb1456a0b9e (diff) | |
| download | linux-0ffb8a4c96e55ecf0e572aec1a0220af3da84e22.tar.xz | |
Merge tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT Bindings:
- Convert and add a bunch of IBM FSI related bindings
- Add a new schema listing legacy compatibles which will (probably)
never be documented. This will silence various checks warning about
them.
- Add bindings for Sierra Wireless mangOH Green SPI IoT interface,
new Arm 2024 Cortex and Neoverse CPUs, QCom sc8180x PDC, QCom SDX75
GPI DMA, imx8mp/imx8qxp fsl,irqsteer, and Renesas RZ/G2UL CRU and
CSI-2 blocks
- Convert Spreadtrum sprd-timer, FSL cpm_qe, FSL fsl,ls-scfg-msi, FSL
q(b)man-*, FSL qoriq-mc, and img,pdc-wdt bindings to DT schema
- Drop obsolete stericsson,abx500.txt
DT core:
- Update dtc to upstream version v1.7.0-93-g1df7b047fe43
- Add support to run DT validation on DTs with applied overlays
- Add helper for creating boolean properties in dynamic nodes and use
that for dynamic PCI nodes
- Clean-up early parsing of '#{address,size}-cells'"
* tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits)
dt-bindings: timer: sprd-timer: convert to YAML
dt-bindings: incomplete-devices: document devices without bindings
dt-bindings: trivial-devices: document the Sierra Wireless mangOH Green SPI IoT interface
scripts/dtc: Update to upstream version v1.7.0-93-g1df7b047fe43
dt-bindings: soc: fsl: Add fsl,ls1028a-reset for reset syscon node
dt-bindings: soc: fsl: cpm_qe: convert to yaml format
dt-bindings: i2c: i2c-fsi: Convert to json-schema
dt-bindings: fsi: Document the FSI Hub Controller
dt-bindings: fsi: Document the AST2700 FSI controller
dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
dt-bindings: fsi: Document the FSI controller common properties
dt-bindings: fsi: Document the IBM SBEFIFO engine
dt-bindings: fsi: p9-occ: Convert to json-schema
dt-bindings: fsi: Document the IBM SCOM engine
dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
dt-bindings: interrupt-controller: convert fsl,ls-scfg-msi to yaml
dt-bindings: soc: fsl: Convert q(b)man-* to yaml format
dt-bindings: misc: fsl,qoriq-mc: convert to yaml format
dt-bindings: drop stale Anson Huang from maintainers
...
Diffstat (limited to 'Documentation/devicetree')
74 files changed, 1977 insertions, 1113 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index cc5a21b47e26..f308ff6c3532 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -147,6 +147,7 @@ properties: - arm,cortex-a710 - arm,cortex-a715 - arm,cortex-a720 + - arm,cortex-a725 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -161,10 +162,15 @@ properties: - arm,cortex-x2 - arm,cortex-x3 - arm,cortex-x4 + - arm,cortex-x925 - arm,neoverse-e1 - arm,neoverse-n1 - arm,neoverse-n2 + - arm,neoverse-n3 - arm,neoverse-v1 + - arm,neoverse-v2 + - arm,neoverse-v3 + - arm,neoverse-v3ae - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml index 526f508cb98d..bd39cf107f3e 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX7ULP System Integration Module maintainers: - - Anson Huang <anson.huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | The system integration module (SIM) provides system control and chip configuration diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml index bae4fcb3aacc..cd3c04c883df 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 Quad Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml index c85ff6ea3d24..6713bbb14f30 100644 --- a/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 SoloLite Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml index 6b549ed1493c..6d64cf9463c9 100644 --- a/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 SLL Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml index 55dcad18b7c6..77afa4b81cf7 100644 --- a/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 SoloX Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml index be54d4df5afa..d57e18a210cc 100644 --- a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 UltraLite Clock Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/imx7d-clock.yaml b/Documentation/devicetree/bindings/clock/imx7d-clock.yaml index e7d8427e4957..880d602d09f4 100644 --- a/Documentation/devicetree/bindings/clock/imx7d-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx7d-clock.yaml @@ -8,7 +8,6 @@ title: Freescale i.MX7 Dual Clock Controller maintainers: - Frank Li <Frank.Li@nxp.com> - - Anson Huang <Anson.Huang@nxp.com> description: | The clock consumer should specify the desired clock by having the clock diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml index 80539f88bc27..c643d4a81478 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP i.MX8M Family Clock Control Module maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Abel Vesa <abelvesa@kernel.org> + - Peng Fan <peng.fan@nxp.com> description: | NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock diff --git a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt b/Documentation/devicetree/bindings/clock/stericsson,abx500.txt deleted file mode 100644 index dbaa886b223e..000000000000 --- a/Documentation/devicetree/bindings/clock/stericsson,abx500.txt +++ /dev/null @@ -1,20 +0,0 @@ -Clock bindings for ST-Ericsson ABx500 clocks - -Required properties : -- compatible : shall contain the following: - "stericsson,ab8500-clk" -- #clock-cells should be <1> - -The ABx500 clocks need to be placed as a subnode of an AB8500 -device node, see mfd/ab8500.txt - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/ste-ab8500.h header and can be used in device -tree sources. - -Example: - -clock-controller { - compatible = "stericsson,ab8500-clk"; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml index 1e08648f5bc7..bbaaa783d184 100644 --- a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -21,7 +21,9 @@ properties: items: - const: lg,sw43408 - reg: true + reg: + maxItems: 1 + port: true vddi-supply: true vpnl-supply: true diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm69380.yaml b/Documentation/devicetree/bindings/display/panel/raydium,rm69380.yaml index b17765b2b351..ec445ff5631c 100644 --- a/Documentation/devicetree/bindings/display/panel/raydium,rm69380.yaml +++ b/Documentation/devicetree/bindings/display/panel/raydium,rm69380.yaml @@ -28,6 +28,9 @@ properties: to work with the indicated panel. The raydium,rm69380 compatible shall always be provided as a fallback. + reg: + maxItems: 1 + avdd-supply: description: Analog voltage rail @@ -38,8 +41,6 @@ properties: maxItems: 1 description: phandle of gpio for reset line - This should be active low - reg: true - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index deb64cb9ca3e..4df4e61895d2 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -27,6 +27,7 @@ properties: - qcom,qcm2290-gpi-dma - qcom,qdu1000-gpi-dma - qcom,sc7280-gpi-dma + - qcom,sdx75-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma diff --git a/Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml b/Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml new file mode 100644 index 000000000000..dfcc2fafa68d --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed FSI master + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The AST2600 and later contain two identical FSI masters. They share a + clock and have a separate interrupt line and output pins. + +properties: + compatible: + enum: + - aspeed,ast2600-fsi-master + - aspeed,ast2700-fsi-master + + clocks: + maxItems: 1 + + cfam-reset-gpios: + maxItems: 1 + description: + Output GPIO pin for CFAM reset + + fsi-routing-gpios: + maxItems: 1 + description: + Output GPIO pin for setting the FSI mux (internal or cabled) + + fsi-mux-gpios: + maxItems: 1 + description: + Input GPIO pin for detecting the desired FSI mux state + + interrupts: + maxItems: 1 + +if: + properties: + compatible: + contains: + enum: + - aspeed,ast2600-fsi-master +then: + properties: + reg: + maxItems: 1 +else: + properties: + reg: + minItems: 1 + items: + - description: OPB control registers + - description: FSI controller registers + - description: FSI link address space + reg-names: + items: + - const: opb + - const: ctrl + - const: fsi + +required: + - compatible + - reg + - clocks + - interrupts + +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/ast2600-clock.h> + #include <dt-bindings/gpio/aspeed-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + fsi-master@1e79b000 { + compatible = "aspeed,ast2600-fsi-master"; + reg = <0x1e79b000 0x94>; + #address-cells = <2>; + #size-cells = <0>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi1_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + }; + }; + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + fsi-master@21800000 { + compatible = "aspeed,ast2700-fsi-master"; + reg = <0x0 0x21800000 0x0 0x100>, + <0x0 0x21000000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x1000000>; + reg-names = "opb", "ctrl", "fsi"; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = <&intc 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi0_default>; + clocks = <&syscon 40>; + }; + }; diff --git a/Documentation/devicetree/bindings/fsi/fsi-controller.yaml b/Documentation/devicetree/bindings/fsi/fsi-controller.yaml new file mode 100644 index 000000000000..ffe191921b26 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/fsi-controller.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/fsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FSI Controller Common Properties + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + FSI (FRU (Field Replaceable Unit) Service Interface) is a two wire bus. The + FSI bus is connected to a CFAM (Common FRU Access Macro) which contains + various engines such as I2C controllers, SPI controllers, etc. + +properties: + "#address-cells": + const: 2 + + "#size-cells": + const: 0 + + '#interrupt-cells': + const: 1 + + bus-frequency: + minimum: 1 + maximum: 200000000 + + interrupt-controller: true + + no-scan-on-init: + $ref: /schemas/types.yaml#/definitions/flag + description: + The FSI controller cannot scan the bus during initialization. + +patternProperties: + "cfam@[0-9a-f],[0-9a-f]": + type: object + properties: + chip-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Processor index, a global unique chip ID which is used to identify + the physical location of the chip in a system specific way. + + bus-frequency: + minimum: 1 + maximum: 100000000 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + required: + - reg + + additionalProperties: true + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt b/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt deleted file mode 100644 index 9853fefff5d8..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi-master-aspeed.txt +++ /dev/null @@ -1,36 +0,0 @@ -Device-tree bindings for AST2600 FSI master -------------------------------------------- - -The AST2600 contains two identical FSI masters. They share a clock and have a -separate interrupt line and output pins. - -Required properties: - - compatible: "aspeed,ast2600-fsi-master" - - reg: base address and length - - clocks: phandle and clock number - - interrupts: platform dependent interrupt description - - pinctrl-0: phandle to pinctrl node - - pinctrl-names: pinctrl state - -Optional properties: - - cfam-reset-gpios: GPIO for CFAM reset - - - fsi-routing-gpios: GPIO for setting the FSI mux (internal or cabled) - - fsi-mux-gpios: GPIO for detecting the desired FSI mux state - - -Examples: - - fsi-master { - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; - reg = <0x1e79b000 0x94>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fsi1_default>; - clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; - - fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; - fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; - - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml b/Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml index e2ca0b000471..ad5c83f48425 100644 --- a/Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml +++ b/Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml @@ -9,11 +9,10 @@ title: IBM FSI-attached SPI controllers maintainers: - Eddie James <eajames@linux.ibm.com> -description: | +description: This binding describes an FSI CFAM engine called the FSI2SPI. Therefore this - node will always be a child of an FSI CFAM node; see fsi.txt for details on - FSI slave and CFAM nodes. This FSI2SPI engine provides access to a number of - SPI controllers. + node will always be a child of an FSI CFAM node. This FSI2SPI engine provides + access to a number of SPI controllers. properties: compatible: @@ -24,6 +23,17 @@ properties: items: - description: FSI slave address + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^spi@[0-9a-f]+$": + type: object + $ref: /schemas/spi/ibm,spi-fsi.yaml + required: - compatible - reg @@ -35,4 +45,22 @@ examples: fsi2spi@1c00 { compatible = "ibm,fsi2spi"; reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + spi@0 { + compatible = "ibm,spi-fsi"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <1000000>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml b/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml index 442cecdc57cb..e49ace3ca339 100644 --- a/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml +++ b/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml @@ -26,7 +26,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml new file mode 100644 index 000000000000..29ea80ff915e --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-fsi-controller.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-fsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached FSI Hub Controller + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The FSI Hub Controller is an FSI controller, providing a number of FSI links, + located on a CFAM. Therefore this node will always be a child of an FSI CFAM + node. + +properties: + compatible: + enum: + - ibm,p9-fsi-controller + + reg: + items: + - description: FSI slave address + +allOf: + - $ref: fsi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + fsi@3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt deleted file mode 100644 index e73358075a90..000000000000 --- a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt +++ /dev/null @@ -1,16 +0,0 @@ -Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC) ------------------------------------------------------------------------------ - -This is the binding for the P9 or P10 On-Chip Controller accessed over FSI from -a service processor. See fsi.txt for details on bindings for FSI slave and CFAM -nodes. The OCC is not an FSI slave device itself, rather it is accessed -through the SBE FIFO. - -Required properties: - - compatible = "ibm,p9-occ" or "ibm,p10-occ" - -Examples: - - occ { - compatible = "ibm,p9-occ"; - }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml new file mode 100644 index 000000000000..537eac70447c --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-occ.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached On-Chip Controller (OCC) + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The POWER processor On-Chip Controller (OCC) helps manage power and + thermals for the system, accessed through the FSI-attached SBEFIFO + from a service processor. + +properties: + compatible: + enum: + - ibm,p9-occ + - ibm,p10-occ + + hwmon: + type: object + $ref: /schemas/hwmon/ibm,occ-hwmon.yaml + +required: + - compatible + +additionalProperties: false + +examples: + - | + occ { + compatible = "ibm,p9-occ"; + + hwmon { + compatible = "ibm,p9-occ-hwmon"; + }; + }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml new file mode 100644 index 000000000000..3cd966fb3c0d --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-sbefifo.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-sbefifo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached SBEFIFO engine + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The SBEFIFO is an FSI CFAM engine that provides an interface to the + POWER processor Self Boot Engine (SBE). This node will always be a child + of an FSI CFAM node. + +properties: + compatible: + enum: + - ibm,p9-sbefifo + - ibm,odyssey-sbefifo + + reg: + items: + - description: FSI slave address + + occ: + type: object + $ref: ibm,p9-occ.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fsi-slave-engine@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p9-occ"; + }; + }; diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml b/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml new file mode 100644 index 000000000000..8cd14a70bedf --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,p9-scom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached SCOM engine + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + The SCOM engine is an interface to the POWER processor PIB (Pervasive + Interconnect Bus). This node will always be a child of an FSI CFAM node. + +properties: + compatible: + enum: + - ibm,p9-scom + - ibm,i2cr-scom + + reg: + items: + - description: FSI slave address + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + scom@1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml index 918776d16ef3..e1fc8bb6d379 100644 --- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX/MXC GPIO controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml index dfa1133f8c5e..8ff54369d16c 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml @@ -8,7 +8,6 @@ title: Freescale MXS GPIO controller maintainers: - Shawn Guo <shawnguo@kernel.org> - - Anson Huang <Anson.Huang@nxp.com> description: | The Freescale MXS GPIO controller is part of MXS PIN controller. diff --git a/Documentation/devicetree/bindings/i2c/i2c-fsi.txt b/Documentation/devicetree/bindings/i2c/i2c-fsi.txt deleted file mode 100644 index b1be2ceb7e69..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-fsi.txt +++ /dev/null @@ -1,40 +0,0 @@ -Device-tree bindings for FSI-attached I2C master and busses ------------------------------------------------------------ - -Required properties: - - compatible = "ibm,i2c-fsi"; - - reg = < address size >; : The FSI CFAM address and address - space size. - - #address-cells = <1>; : Number of address cells in child - nodes. - - #size-cells = <0>; : Number of size cells in child nodes. - - child nodes : Nodes to describe busses off the I2C - master. - -Child node required properties: - - reg = < port number > : The port number on the I2C master. - -Child node optional properties: - - child nodes : Nodes to describe devices on the I2C - bus. - -Examples: - - i2c@1800 { - compatible = "ibm,i2c-fsi"; - reg = < 0x1800 0x400 >; - #address-cells = <1>; - #size-cells = <0>; - - i2c-bus@0 { - reg = <0>; - }; - - i2c-bus@1 { - reg = <1>; - - eeprom@50 { - compatible = "vendor,dev-name"; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml index 54d500be6aaa..1dcb9c78de3b 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Low Power Inter IC (LPI2C) for i.MX maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml b/Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml new file mode 100644 index 000000000000..40ea82942e4d --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/ibm,i2c-fsi.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/ibm,i2c-fsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM FSI-attached I2C controller + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: + This I2C controller is an FSI CFAM engine, providing access to a number of + I2C busses. Therefore this node will always be a child of an FSI CFAM node. + +properties: + compatible: + enum: + - ibm,i2c-fsi + + reg: + items: + - description: FSI slave address + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^i2c-bus@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + + allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + + unevaluatedProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c@1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + i2c-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/fsl,mag3110.yaml b/Documentation/devicetree/bindings/iio/magnetometer/fsl,mag3110.yaml index 6b54d32323fc..fbe8c2eb0857 100644 --- a/Documentation/devicetree/bindings/iio/magnetometer/fsl,mag3110.yaml +++ b/Documentation/devicetree/bindings/iio/magnetometer/fsl,mag3110.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale MAG3110 magnetometer sensor maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Jonathan Cameron <jic23@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/incomplete-devices.yaml b/Documentation/devicetree/bindings/incomplete-devices.yaml new file mode 100644 index 000000000000..cfc1d39441b1 --- /dev/null +++ b/Documentation/devicetree/bindings/incomplete-devices.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/incomplete-devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rejected, Legacy or Incomplete Devices + +maintainers: + - Rob Herring <robh@kernel.org> + +description: + Some devices will not or should not get a proper Devicetree bindings, but + their compatibles are present in Linux drivers for various reasons. + + Examples are devices using ACPI PRP0001 with non-updatable firmware/ACPI + tables or old PowerPC platforms without in-tree DTS. + + Following list of devices is an incomplete schema with a goal to pass DT schema + checks on undocumented compatibles but also reject any DTS file using such + un-approved compatible. + + Usage of any of following compatibles is not allowed in Devicetree sources, + even if they come from immutable firmware. + +properties: + compatible: + oneOf: + - description: + Rejected compatibles in Devicetree, but used in ACPI-based devices + with non-updatable firmware/ACPI tables (via ACPI PRP0001) + enum: + - broadcom,bcm5241 + - ltr,ltrf216a + + - description: Legacy compatibles used on Macintosh devices + enum: + - adm1030 + - bmac+ + - heathrow-media-bay + - keylargo-media-bay + - lm87cimt + - MAC,adm1030 + - MAC,ds1775 + - max6690 + - ohare-media-bay + - ohare-swim3 + - smu-sat + - swim3 + + - description: Legacy compatibles used on other PowerPC devices + enum: + - 1682m-rng + - IBM,lhca + - IBM,lhea + - IBM,lhea-ethernet + - mpc5200b-fec-phy + - mpc5200-serial + - mpc5200-sram + - ohci-be + - ohci-bigendian + - ohci-le + + - description: Legacy compatibles used on SPARC devices + enum: + - bq4802 + - ds1287 + - isa-m5819p + - isa-m5823p + - m5819 + - sab82532 + - SUNW,bbc-beep + - SUNW,bbc-i2c + - SUNW,CS4231 + - SUNW,ebus-pic16f747-env + - SUNW,kt-cwq + - SUNW,kt-mau + - SUNW,n2-cwq + - SUNW,n2-mau + - SUNW,niusl + - SUNW,smbus-beep + - SUNW,sun4v-console + - SUNW,sun4v-pci + - SUNW,vf-cwq + - SUNW,vf-mau + + - description: Incomplete and/or legacy compatibles for unknown devices + enum: + - electra-cf + - i2cpcf,8584 + - virtio,uml + + - description: Linux kernel unit tests and sample code + enum: + - audio-graph-card2-custom-sample + - compat1 + - compat2 + - compat3 + - linux,spi-loopback-test + - mailbox-test + - regulator-virtual-consumer + + - description: + Devices on MIPS platform, without any DTS users. These are + unlikely to get converted to DT schema. + enum: + - mti,ranchu + + - description: + Devices on PowerPC platform, without any DTS users. These are + unlikely to get converted to DT schema. + enum: + - fujitsu,coral + - fujitsu,lime + - fujitsu,MB86276 + - fujitsu,MB86277 + - fujitsu,MB86293 + - fujitsu,MB86294 + - fujitsu,mint + - ibm,axon-msic + - ibm,pmemory + - ibm,pmemory-v2 + - ibm,power-rng + - ibm,ppc4xx-spi + - ibm,sdram-4xx-ddr2 + - ibm,secureboot + - ibm,secureboot-v1 + - ibm,secureboot-v2 + - ibm,secvar-backend + - sgy,gpio-halt + - wrs,epld-localbus + +required: + - compatible + - broken-usage-of-incorrect-compatible + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml index 20ad4ad82ad6..aae676ba30ed 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml @@ -14,7 +14,10 @@ properties: oneOf: - const: fsl,imx-irqsteer - items: - - const: fsl,imx8m-irqsteer + - enum: + - fsl,imx8m-irqsteer + - fsl,imx8mp-irqsteer + - fsl,imx8qxp-irqsteer - const: fsl,imx-irqsteer reg: @@ -42,6 +45,9 @@ properties: clock-names: const: ipg + power-domains: + maxItems: 1 + interrupt-controller: true "#interrupt-cells": @@ -70,6 +76,21 @@ required: - fsl,channel - fsl,num-irqs +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mp-irqsteer + - fsl,imx8qxp-irqsteer + then: + required: + - power-domains + else: + properties: + power-domains: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-msi.yaml new file mode 100644 index 000000000000..9ba8d4d73351 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-msi.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape SCFG PCIe MSI controller + +description: | + This interrupt controller hardware is a second level interrupt controller that + is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based + platforms. If interrupt-parent is not provided, the default parent interrupt + controller will be used. + + Each PCIe node needs to have property msi-parent that points to + MSI controller node + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + enum: + - fsl,ls1012a-msi + - fsl,ls1021a-msi + - fsl,ls1043a-msi + - fsl,ls1043a-v1.1-msi + - fsl,ls1046a-msi + + reg: + maxItems: 1 + + '#msi-cells': + const: 1 + + interrupts: + items: + - description: Shared MSI interrupt group 0 + - description: Shared MSI interrupt group 1 + - description: Shared MSI interrupt group 2 + - description: Shared MSI interrupt group 3 + minItems: 1 + +required: + - compatible + - reg + - msi-controller + - interrupts + +allOf: + - $ref: msi-controller.yaml + - if: + properties: + compatible: + contains: + enum: + - fsl,ls1046a-msi + then: + properties: + interrupts: + minItems: 4 + else: + properties: + interrupts: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@1571000 { + compatible = "fsl,ls1043a-msi"; + reg = <0x1571000 0x8>; + msi-controller; + #msi-cells = <1>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt deleted file mode 100644 index 454ce04d6787..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Freescale Layerscape SCFG PCIe MSI controller - -Required properties: - -- compatible: should be "fsl,<soc-name>-msi" to identify - Layerscape PCIe MSI controller block such as: - "fsl,ls1021a-msi" - "fsl,ls1043a-msi" - "fsl,ls1046a-msi" - "fsl,ls1043a-v1.1-msi" - "fsl,ls1012a-msi" -- msi-controller: indicates that this is a PCIe MSI controller node -- reg: physical base address of the controller and length of memory mapped. -- interrupts: an interrupt to the parent interrupt controller. - -This interrupt controller hardware is a second level interrupt controller that -is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based -platforms. If interrupt-parent is not provided, the default parent interrupt -controller will be used. -Each PCIe node needs to have property msi-parent that points to -MSI controller node - -Examples: - - msi1: msi-controller@1571000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>, - msi-controller; - interrupts = <0 116 0x4>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 4bdc8321904b..985fa10abb99 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -30,6 +30,7 @@ properties: - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc + - qcom,sc8180x-pdc - qcom,sc8280xp-pdc - qcom,sdm670-pdc - qcom,sdm845-pdc diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml index 1e72b8808d24..bc1245127025 100644 --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml @@ -19,6 +19,7 @@ properties: compatible: items: - enum: + - renesas,r9a07g043-cru # RZ/G2UL - renesas,r9a07g044-cru # RZ/G2{L,LC} - renesas,r9a07g054-cru # RZ/V2L - const: renesas,rzg2l-cru @@ -87,10 +88,6 @@ properties: Input port node, describing the Image Processing module connected to the CSI-2 receiver. - required: - - port@0 - - port@1 - required: - compatible - reg @@ -102,6 +99,36 @@ required: - reset-names - power-domains +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g044-cru + - renesas,r9a07g054-cru + then: + properties: + ports: + required: + - port@0 + - port@1 + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-cru + then: + properties: + ports: + properties: + port@0: false + + required: + - port@1 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml index 67eea2ac1d22..7faa12fecd5b 100644 --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml @@ -19,6 +19,7 @@ properties: compatible: items: - enum: + - renesas,r9a07g043-csi2 # RZ/G2UL - renesas,r9a07g044-csi2 # RZ/G2{L,LC} - renesas,r9a07g054-csi2 # RZ/V2L - const: renesas,rzg2l-csi2 diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml index 71547eee9919..5447f1dddedf 100644 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Multi Mode DDR controller (MMDC) maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt deleted file mode 100644 index 7b486d4985dc..000000000000 --- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt +++ /dev/null @@ -1,196 +0,0 @@ -* Freescale Management Complex - -The Freescale Management Complex (fsl-mc) is a hardware resource -manager that manages specialized hardware objects used in -network-oriented packet processing applications. After the fsl-mc -block is enabled, pools of hardware resources are available, such as -queues, buffer pools, I/O interfaces. These resources are building -blocks that can be used to create functional hardware objects/devices -such as network interfaces, crypto accelerator instances, L2 switches, -etc. - -For an overview of the DPAA2 architecture and fsl-mc bus see: -Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst - -As described in the above overview, all DPAA2 objects in a DPRC share the -same hardware "isolation context" and a 10-bit value called an ICID -(isolation context id) is expressed by the hardware to identify -the requester. - -The generic 'iommus' property is insufficient to describe the relationship -between ICIDs and IOMMUs, so an iommu-map property is used to define -the set of possible ICIDs under a root DPRC and how they map to -an IOMMU. - -For generic IOMMU bindings, see -Documentation/devicetree/bindings/iommu/iommu.txt. - -For arm-smmu binding, see: -Documentation/devicetree/bindings/iommu/arm,smmu.yaml. - -The MSI writes are accompanied by sideband data which is derived from the ICID. -The msi-map property is used to associate the devices with both the ITS -controller and the sideband data which accompanies the writes. - -For generic MSI bindings, see -Documentation/devicetree/bindings/interrupt-controller/msi.txt. - -For GICv3 and GIC ITS bindings, see: -Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml. - -Required properties: - - - compatible - Value type: <string> - Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex - compatible with this binding must have Block Revision - Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in - the MC control register region. - - - reg - Value type: <prop-encoded-array> - Definition: A standard property. Specifies one or two regions - defining the MC's registers: - - -the first region is the command portal for the - this machine and must always be present - - -the second region is the MC control registers. This - region may not be present in some scenarios, such - as in the device tree presented to a virtual machine. - - - ranges - Value type: <prop-encoded-array> - Definition: A standard property. Defines the mapping between the child - MC address space and the parent system address space. - - The MC address space is defined by 3 components: - <region type> <offset hi> <offset lo> - - Valid values for region type are - 0x0 - MC portals - 0x1 - QBMAN portals - - - #address-cells - Value type: <u32> - Definition: Must be 3. (see definition in 'ranges' property) - - - #size-cells - Value type: <u32> - Definition: Must be 1. - -Sub-nodes: - - The fsl-mc node may optionally have dpmac sub-nodes that describe - the relationship between the Ethernet MACs which belong to the MC - and the Ethernet PHYs on the system board. - - The dpmac nodes must be under a node named "dpmacs" which contains - the following properties: - - - #address-cells - Value type: <u32> - Definition: Must be present if dpmac sub-nodes are defined and must - have a value of 1. - - - #size-cells - Value type: <u32> - Definition: Must be present if dpmac sub-nodes are defined and must - have a value of 0. - - These nodes must have the following properties: - - - compatible - Value type: <string> - Definition: Must be "fsl,qoriq-mc-dpmac". - - - reg - Value type: <prop-encoded-array> - Definition: Specifies the id of the dpmac. - - - phy-handle - Value type: <phandle> - Definition: Specifies the phandle to the PHY device node associated - with the this dpmac. -Optional properties: - -- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier - data. - - The property is an arbitrary number of tuples of - (icid-base,iommu,iommu-base,length). - - Any ICID i in the interval [icid-base, icid-base + length) is - associated with the listed IOMMU, with the iommu-specifier - (i - icid-base + iommu-base). - -- msi-map: Maps an ICID to a GIC ITS and associated msi-specifier - data. - - The property is an arbitrary number of tuples of - (icid-base,gic-its,msi-base,length). - - Any ICID in the interval [icid-base, icid-base + length) is - associated with the listed GIC ITS, with the msi-specifier - (i - icid-base + msi-base). - -Deprecated properties: - - - msi-parent - Value type: <phandle> - Definition: Describes the MSI controller node handling message - interrupts for the MC. When there is no translation - between the ICID and deviceID this property can be used - to describe the MSI controller used by the devices on the - mc-bus. - The use of this property for mc-bus is deprecated. Please - use msi-map. - -Example: - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - #iommu-cells = <1>; - stream-match-mask = <0x7C00>; - ... - }; - - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - ... - } - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - ... - }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - /* define map for ICIDs 23-64 */ - iommu-map = <23 &smmu 23 41>; - /* define msi map for ICIDs 23-64 */ - msi-map = <23 &its 23 41>; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <1>; - phy-handle = <&mdio0_phy0>; - } - } - }; diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml new file mode 100644 index 000000000000..01b00d89a992 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Management Complex + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + The Freescale Management Complex (fsl-mc) is a hardware resource + manager that manages specialized hardware objects used in + network-oriented packet processing applications. After the fsl-mc + block is enabled, pools of hardware resources are available, such as + queues, buffer pools, I/O interfaces. These resources are building + blocks that can be used to create functional hardware objects/devices + such as network interfaces, crypto accelerator instances, L2 switches, + etc. + + For an overview of the DPAA2 architecture and fsl-mc bus see: + Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst + + As described in the above overview, all DPAA2 objects in a DPRC share the + same hardware "isolation context" and a 10-bit value called an ICID + (isolation context id) is expressed by the hardware to identify + the requester. + + The generic 'iommus' property is insufficient to describe the relationship + between ICIDs and IOMMUs, so an iommu-map property is used to define + the set of possible ICIDs under a root DPRC and how they map to + an IOMMU. + + For generic IOMMU bindings, see + Documentation/devicetree/bindings/iommu/iommu.txt. + + For arm-smmu binding, see: + Documentation/devicetree/bindings/iommu/arm,smmu.yaml. + + The MSI writes are accompanied by sideband data which is derived from the ICID. + The msi-map property is used to associate the devices with both the ITS + controller and the sideband data which accompanies the writes. + + For generic MSI bindings, see + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + + For GICv3 and GIC ITS bindings, see: + Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml. + +properties: + compatible: + enum: + - fsl,qoriq-mc + description: + Must be "fsl,qoriq-mc". A Freescale Management Complex + compatible with this binding must have Block Revision + Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in + the MC control register region. + + reg: + items: + - description: + the first region is the command portal for the + this machine and must always be present + + - description: + the second region is the MC control registers. This + region may not be present in some scenarios, such + as in the device tree presented to a virtual machine. + + ranges: + description: | + A standard property. Defines the mapping between the child + MC address space and the parent system address space. + + The MC address space is defined by 3 components: + <region type> <offset hi> <offset lo> + + Valid values for region type are + 0x0 - MC portals + 0x1 - QBMAN portals + + "#address-cells": + const: 3 + + "#size-cells": + const: 1 + + iommu-map: + description: | + Maps an ICID to an IOMMU and associated iommu-specifier + data. + + The property is an arbitrary number of tuples of + (icid-base,iommu,iommu-base,length). + + Any ICID i in the interval [icid-base, icid-base + length) is + associated with the listed IOMMU, with the iommu-specifier + (i - icid-base + iommu-base). + + msi-map: + description: | + Maps an ICID to a GIC ITS and associated msi-specifier + data. + + The property is an arbitrary number of tuples of + (icid-base,gic-its,msi-base,length). + + Any ICID in the interval [icid-base, icid-base + length) is + associated with the listed GIC ITS, with the msi-specifier + (i - icid-base + msi-base). + + msi-parent: + deprecated: true + $ref: /schemas/types.yaml#/definitions/phandle + description: + Describes the MSI controller node handling message + interrupts for the MC. When there is no translation + between the ICID and deviceID this property can be used + to describe the MSI controller used by the devices on the + mc-bus. + The use of this property for mc-bus is deprecated. Please + use msi-map. + + dma-coherent: true + + dpmacs: + type: object + description: + The fsl-mc node may optionally have dpmac sub-nodes that describe + the relationship between the Ethernet MACs which belong to the MC + and the Ethernet PHYs on the system board. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + '^ethernet@[a-f0-9]+$': + $ref: /schemas/net/fsl,qoriq-mc-dpmac.yaml + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x0c000000 0x40>, /* MC portal base */ + <0x08340000 0x40000>; /* MC control reg */ + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x8 0x18000000 0x8000000>; + + /* define map for ICIDs 23-64 */ + iommu-map = <23 &smmu 23 41>; + /* define msi map for ICIDs 23-64 */ + msi-map = <23 &its 23 41>; + #address-cells = <3>; + #size-cells = <1>; + + dpmacs { + #address-cells = <1>; + #size-cells = <0>; + + ethernet@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <1>; + phy-handle = <&mdio0_phy0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/nvmem/imx-iim.yaml b/Documentation/devicetree/bindings/nvmem/imx-iim.yaml index e9d9d8df4811..bb37d72c9eaa 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-iim.yaml +++ b/Documentation/devicetree/bindings/nvmem/imx-iim.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX IC Identification Module (IIM) maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | This binding represents the IC Identification Module (IIM) found on diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml index be1314454bec..e21c06e9a741 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX On-Chip OTP Controller (OCOTP) maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | This binding represents the on-chip eFuse OTP controller found on diff --git a/Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml index d9287be89877..95121dd6311c 100644 --- a/Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml +++ b/Documentation/devicetree/bindings/nvmem/mxs-ocotp.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: On-Chip OTP Memory for Freescale i.MX23/i.MX28 maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: nvmem.yaml# diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml index 8bef9dfeba9a..ac0a35bf8648 100644 --- a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX TPM PWM controller maintainers: - - Anson Huang <anson.huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | The TPM counter and period counter are shared between multiple diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml b/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml index 8f50e23ca8c9..a9d3a41ac5b9 100644 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.yaml @@ -8,7 +8,6 @@ title: Freescale MXS PWM controller maintainers: - Shawn Guo <shawnguo@kernel.org> - - Anson Huang <anson.huang@nxp.com> allOf: - $ref: pwm.yaml# diff --git a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt deleted file mode 100644 index 2a00e14e11e0..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt +++ /dev/null @@ -1,56 +0,0 @@ -QorIQ DPAA Buffer Manager Portals Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - BMan Portal - - Example - -BMan Portal Node - -Portals are memory mapped interfaces to BMan that allow low-latency, lock-less -interaction by software running on processor cores, accelerators and network -interfaces with the BMan - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,bman-portal-<hardware revision>" - May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Two regions. The first is the cache-enabled region of - the portal. The second is the cache-inhibited region of - the portal - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property - -EXAMPLE - -The example below shows a (P4080) BMan portals container/bus node with two portals - - bman-portals@ff4000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0xf 0xf4000000 0x200000>; - - bman-portal@0 { - compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; - reg = <0x0 0x4000>, <0x100000 0x1000>; - interrupts = <105 2 0 0>; - }; - bman-portal@4000 { - compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <107 2 0 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt b/Documentation/devicetree/bindings/soc/fsl/bman.txt deleted file mode 100644 index 48eed140765b..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/bman.txt +++ /dev/null @@ -1,137 +0,0 @@ -QorIQ DPAA Buffer Manager Device Tree Bindings - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - BMan Node - - BMan Private Memory Node - - Example - -BMan Node - -The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). -BMan supports hardware allocation and deallocation of buffers belonging to pools -originally created by software with configurable depletion thresholds. This -binding covers the CCSR space programming model - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,bman" - May include "fsl,<SoC>-bman" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Registers region within the CCSR address space - -The BMan revision information is located in the BMAN_IP_REV_1/2 registers which -are located at offsets 0xbf8 and 0xbfc - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property. The error interrupt - -- fsl,bman-portals - Usage: Required - Value type: <phandle> - Definition: Phandle to this BMan instance's portals - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -Devices connected to a BMan instance via Direct Connect Portals (DCP) must link -to the respective BMan instance - -- fsl,bman - Usage: Required - Value type: <prop-encoded-array> - Description: List of phandle and DCP index pairs, to the BMan instance - to which this device is connected via the DCP - -BMan Private Memory Node - -BMan requires a contiguous range of physical memory used for the backing store -for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as -a node under the /reserved-memory node. - -The BMan FBPR memory node must be named "bman-fbpr" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,bman-fbpr" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The following constraints are relevant to the FBPR private memory: - - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to - 16 GiB - - The alignment must be a muliptle of the memory size - -The size of the FBPR must be chosen by observing the hardware features configured -via the Reset Configuration Word (RCW) and that are relevant to a specific board -(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports, -etc.). The size configured in the DT must reflect the hardware capabilities and -not the specific needs of an application - -For additional details about reserved memory regions see reserved-memory.txt - -EXAMPLE - -The example below shows a BMan FBPR dynamic allocation memory node - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bman_fbpr: bman-fbpr { - compatible = "shared-mem-pool"; - size = <0 0x1000000>; - alignment = <0 0x1000000>; - no-map; - }; - }; - -The example below shows a (P4080) BMan CCSR-space node - - bportals: bman-portals@ff4000000 { - ... - }; - - crypto@300000 { - ... - fsl,bman = <&bman, 2>; - ... - }; - - bman: bman@31a000 { - compatible = "fsl,bman"; - reg = <0x31a000 0x1000>; - interrupts = <16 2 1 2>; - fsl,liodn = <0x17>; - fsl,bman-portals = <&bportals>; - memory-region = <&bman_fbpr>; - }; - - fman@400000 { - ... - fsl,bman = <&bman, 0>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml new file mode 100644 index 000000000000..53b07d4edc77 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Firmware Node + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + This node defines a firmware binary that is embedded in the device tree, for + the purpose of passing the firmware from bootloader to the kernel, or from + the hypervisor to the guest. + + The firmware node itself contains the firmware binary contents, a compatible + property, and any firmware-specific properties. The node should be placed + inside a QE node that needs it. Doing so eliminates the need for a + fsl,firmware-phandle property. Other QE nodes that need the same firmware + should define an fsl,firmware-phandle property that points to the firmware node + in the first QE node. + + The fsl,firmware property can be specified in the DTS (possibly using incbin) + or can be inserted by the boot loader at boot time. + +properties: + compatible: + enum: + - fsl,qe-firmware + + fsl,firmware: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + A standard property. This property contains the firmware binary "blob". + +required: + - compatible + - fsl,firmware + +additionalProperties: false + +examples: + - | + qe-firmware { + compatible = "fsl,qe-firmware"; + fsl,firmware = <0x70 0xcd 0x00 0x00 0x01 0x46 0x45>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml new file mode 100644 index 000000000000..8267ad00727b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Interrupt Controller (IC) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,qe-ic + + reg: + maxItems: 1 + + interrupts: + items: + - description: QE interrupt + - description: QE critical + - description: QE error + minItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <95 2 0 0 94 2 0 0>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml new file mode 100644 index 000000000000..cf0f38dbbe0d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine Multi-User RAM (MURAM) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: Multi-User RAM (MURAM) + +properties: + compatible: + items: + - const: fsl,qe-muram + - const: fsl,cpm-muram + + ranges: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, slave] + + +patternProperties: + '^data\-only@[a-f0-9]+$': + type: object + properties: + compatible: + items: + - const: fsl,qe-muram-data + - const: fsl,cpm-muram-data + + reg: + maxItems: 1 + + required: + - compatible + - reg + + additionalProperties: false + +required: + - compatible + - ranges + +additionalProperties: false + +examples: + - | + muram@10000 { + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x00010000 0x0000c000>; + #address-cells = <1>; + #size-cells = <1>; + + data-only@0{ + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml new file mode 100644 index 000000000000..8e58ab58c063 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-si.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Serial Interface Block (SI) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The SI manages the routing of eight TDM lines to the QE block serial drivers, + the MCC and the UCCs, for receive and transmit. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,ls1043-qe-si + - const: fsl,t1040-qe-si + - enum: + - fsl,t1040-qe-si + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml new file mode 100644 index 000000000000..cc4ed48d786c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-siram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Serial Interface Block RAM(SIRAM) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + store the routing entries of SI + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,ls1043-qe-siram + - const: fsl,t1040-qe-siram + - const: fsl,t1040-qe-siram + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml new file mode 100644 index 000000000000..89cdf5e1d0a8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module (QE) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + This represents qe module that is installed on PowerQUICC II Pro. + + NOTE: This is an interim binding; it should be updated to fit + in with the CPM binding later in this document. + + Basically, it is a bus of devices, that could act more or less + as a complete entity (UCC, USB etc ). All of them should be siblings on + the "root" qe node, using the common properties from there. + The description below applies to the qe of MPC8360 and + more nodes and properties would be extended in the future. + +properties: + compatible: + items: + - const: fsl,qe + - const: simple-bus + + reg: + maxItems: 1 + + ranges: + maxItems: 1 + + model: + $ref: /schemas/types.yaml#/definitions/string + enum: [QE, CPM, CPM2] + + bus-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: the clock frequency for QUICC Engine. + + fsl,qe-num-riscs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: define how many RISC engines the QE has. + + fsl,qe-snums: + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 28 + description: + defining the array of serial number (SNUM) values for the virtual + threads. + + fsl,firmware-phandle: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + required only if there is no fsl,qe-firmware child node + + Points to a firmware node (see "QE Firmware Node" below) + that contains the firmware that should be uploaded for this QE. + The compatible property for the firmware node should say, + "fsl,qe-firmware". + + brg-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + the internal clock source frequency for baud-rate + generators in Hz. + + fsl,qe-num-snums: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: | + define how many serial number(SNUM) the QE can use + for the threads. Use fsl,qe-snums instead to not only specify the + number of snums, but also their values. + +patternProperties: + '^muram@[a-f0-9]+$': + $ref: fsl,qe-muram.yaml + + '^interrupt-controller@[a-f0-9]+$': + $ref: fsl,qe-ic.yaml + + '^si@[a-f0-9]+$': + $ref: fsl,qe-si.yaml + + '^siram@[a-f0-9]+$': + $ref: fsl,qe-siram.yaml + +required: + - compatible + - reg + - bus-frequency + +allOf: + - $ref: /schemas/simple-bus.yaml# + +unevaluatedProperties: false + +examples: + - | + qe-bus@e0100000 { + compatible = "fsl,qe", "simple-bus"; + reg = <0xe0100000 0x480>; + ranges = <0 0xe0100000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + brg-frequency = <0>; + bus-frequency = <0x179a7b00>; + fsl,qe-snums = /bits/ 8 < + 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d + 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89 + 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9 + 0xd8 0xd9 0xe8 0xe9>; + + interrupt-controller@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <95 2 0 0 94 2 0 0>; + }; + + si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + muram@10000 { + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x00010000 0x0000c000>; + #address-cells = <1>; + #size-cells = <1>; + + data-only@0{ + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt deleted file mode 100644 index 05ec2a838c54..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt +++ /dev/null @@ -1,178 +0,0 @@ -* Freescale QUICC Engine module (QE) -This represents qe module that is installed on PowerQUICC II Pro. - -NOTE: This is an interim binding; it should be updated to fit -in with the CPM binding later in this document. - -Basically, it is a bus of devices, that could act more or less -as a complete entity (UCC, USB etc ). All of them should be siblings on -the "root" qe node, using the common properties from there. -The description below applies to the qe of MPC8360 and -more nodes and properties would be extended in the future. - -i) Root QE device - -Required properties: -- compatible : should be "fsl,qe"; -- model : precise model of the QE, Can be "QE", "CPM", or "CPM2" -- reg : offset and length of the device registers. -- bus-frequency : the clock frequency for QUICC Engine. -- fsl,qe-num-riscs: define how many RISC engines the QE has. -- fsl,qe-snums: This property has to be specified as '/bits/ 8' value, - defining the array of serial number (SNUM) values for the virtual - threads. - -Optional properties: -- fsl,firmware-phandle: - Usage: required only if there is no fsl,qe-firmware child node - Value type: <phandle> - Definition: Points to a firmware node (see "QE Firmware Node" below) - that contains the firmware that should be uploaded for this QE. - The compatible property for the firmware node should say, - "fsl,qe-firmware". - -Recommended properties -- brg-frequency : the internal clock source frequency for baud-rate - generators in Hz. - -Deprecated properties -- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use - for the threads. Use fsl,qe-snums instead to not only specify the - number of snums, but also their values. - -Example: - qe@e0100000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - compatible = "fsl,qe"; - ranges = <0 e0100000 00100000>; - reg = <e0100000 480>; - brg-frequency = <0>; - bus-frequency = <179A7B00>; - fsl,qe-snums = /bits/ 8 < - 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D - 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89 - 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9 - 0xD8 0xD9 0xE8 0xE9>; - } - -* Multi-User RAM (MURAM) - -Required properties: -- compatible : should be "fsl,qe-muram", "fsl,cpm-muram". -- mode : the could be "host" or "slave". -- ranges : Should be defined as specified in 1) to describe the - translation of MURAM addresses. -- data-only : sub-node which defines the address area under MURAM - bus that can be allocated as data/parameter - -Example: - - muram@10000 { - compatible = "fsl,qe-muram", "fsl,cpm-muram"; - ranges = <0 00010000 0000c000>; - - data-only@0{ - compatible = "fsl,qe-muram-data", - "fsl,cpm-muram-data"; - reg = <0 c000>; - }; - }; - -* Interrupt Controller (IC) - -Required properties: -- compatible : should be "fsl,qe-ic". -- reg : Address range of IC register set. -- interrupts : interrupts generated by the device. -- interrupt-controller : this device is a interrupt controller. - -Example: - - qeic: interrupt-controller@80 { - interrupt-controller; - compatible = "fsl,qe-ic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0x80 0x80>; - interrupts = <95 2 0 0 94 2 0 0>; - }; - -* Serial Interface Block (SI) - -The SI manages the routing of eight TDM lines to the QE block serial drivers -, the MCC and the UCCs, for receive and transmit. - -Required properties: -- compatible : must be "fsl,<chip>-qe-si". For t1040, must contain - "fsl,t1040-qe-si". -- reg : Address range of SI register set. - -Example: - - si1: si@700 { - compatible = "fsl,t1040-qe-si"; - reg = <0x700 0x80>; - }; - -* Serial Interface Block RAM(SIRAM) - -store the routing entries of SI - -Required properties: -- compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain - "fsl,t1040-qe-siram". -- reg : Address range of SI RAM. - -Example: - - siram1: siram@1000 { - compatible = "fsl,t1040-qe-siram"; - reg = <0x1000 0x800>; - }; - -* QE Firmware Node - -This node defines a firmware binary that is embedded in the device tree, for -the purpose of passing the firmware from bootloader to the kernel, or from -the hypervisor to the guest. - -The firmware node itself contains the firmware binary contents, a compatible -property, and any firmware-specific properties. The node should be placed -inside a QE node that needs it. Doing so eliminates the need for a -fsl,firmware-phandle property. Other QE nodes that need the same firmware -should define an fsl,firmware-phandle property that points to the firmware node -in the first QE node. - -The fsl,firmware property can be specified in the DTS (possibly using incbin) -or can be inserted by the boot loader at boot time. - -Required properties: - - compatible - Usage: required - Value type: <string> - Definition: A standard property. Specify a string that indicates what - kind of firmware it is. For QE, this should be "fsl,qe-firmware". - - - fsl,firmware - Usage: required - Value type: <prop-encoded-array>, encoded as an array of bytes - Definition: A standard property. This property contains the firmware - binary "blob". - -Example: - qe1@e0080000 { - compatible = "fsl,qe"; - qe_firmware:qe-firmware { - compatible = "fsl,qe-firmware"; - fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...]; - }; - ... - }; - - qe2@e0090000 { - compatible = "fsl,qe"; - fsl,firmware-phandle = <&qe_firmware>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml new file mode 100644 index 000000000000..8dce75bebff9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,bman-portal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager Portals + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + QorIQ DPAA Buffer Manager Portal + + Portals are memory mapped interfaces to BMan that allow low-latency, lock-less + interaction by software running on processor cores, accelerators and network + interfaces with the BMan + +properties: + compatible: + oneOf: + - const: fsl,bman-portal + - items: + - enum: + - fsl,bman-portal-1.0.0 + - fsl,ls1043a-bmap-portal + - fsl,ls1046a-bmap-portal + - const: fsl,bman-portal + reg: + items: + - description: the cache-enabled region of the portal + - description: the cache-inhibited region of the portal + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + bman-portal@0 { + compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; + reg = <0x0 0x4000>, <0x100000 0x1000>; + interrupts = <105 IRQ_TYPE_EDGE_FALLING 0 0>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml new file mode 100644 index 000000000000..e6f468264b8d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,bman.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Buffer Manager + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). + BMan supports hardware allocation and deallocation of buffers belonging to + pools originally created by software with configurable depletion thresholds. + This binding covers the CCSR space programming model + +properties: + compatible: + oneOf: + - const: fsl,bman + - items: + - enum: + - fsl,ls1043a-bman + - fsl,ls1046a-bman + - const: fsl,bman + + reg: + items: + - description: | + Registers region within the CCSR address space + + The BMan revision information is located in the BMAN_IP_REV_1/2 + registers which are located at offsets 0xbf8 and 0xbfc + + interrupts: + items: + - description: The error interrupt + + memory-region: + minItems: 1 + maxItems: 2 + description: + List of phandles referencing the BMan private memory + nodes (described below). The bman-fqd node must be + first followed by bman-pfdr node. Only used on ARM + + Devices connected to a BMan instance via Direct Connect Portals (DCP) must link + to the respective BMan instance + + fsl,bman-portals: + $ref: /schemas/types.yaml#/definitions/phandle + description: ref fsl,bman-port.yaml + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + See pamu.txt, PAMU property used for dynamic LIODN assignment + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + bman@31a000 { + compatible = "fsl,bman"; + reg = <0x31a000 0x1000>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 2>; + fsl,liodn = <0x17>; + fsl,bman-portals = <&bportals>; + memory-region = <&bman_fbpr>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml new file mode 100644 index 000000000000..31295be91013 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas//soc/fsl/fsl,ls1028a-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape Reset Registers Module + +maintainers: + - Frank Li + +description: + Reset Module includes chip reset, service processor control and Reset Control + Word (RCW) status. + +properties: + $nodename: + pattern: "^syscon@[0-9a-f]+$" + + compatible: + items: + - enum: + - fsl,ls1028a-reset + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + little-endian: true + + reboot: + $ref: /schemas/power/reset/syscon-reboot.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - reboot + +additionalProperties: false + +examples: + - | + syscon@1e60000 { + compatible = "fsl,ls1028a-reset", "syscon", "simple-mfd"; + reg = <0x1e60000 0x10000>; + little-endian; + + reboot { + compatible = "syscon-reboot"; + offset = <0>; + mask = <0x02>; + }; + }; + diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml new file mode 100644 index 000000000000..de0b4ae740ff --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman-fqd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QMan Private Memory Nodes + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + QMan requires two contiguous range of physical memory used for the backing store + for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). + This memory is reserved/allocated as a node under the /reserved-memory node. + + BMan requires a contiguous range of physical memory used for the backing store + for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as + a node under the /reserved-memory node. + + The QMan FQD memory node must be named "qman-fqd" + The QMan PFDR memory node must be named "qman-pfdr" + The BMan FBPR memory node must be named "bman-fbpr" + + The following constraints are relevant to the FQD and PFDR private memory: + - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to + 1 GiB + - The alignment must be a muliptle of the memory size + + The size of the FQD and PFDP must be chosen by observing the hardware features + configured via the Reset Configuration Word (RCW) and that are relevant to a + specific board (e.g. number of MAC(s) pinned-out, number of offline/host command + FMan ports, etc.). The size configured in the DT must reflect the hardware + capabilities and not the specific needs of an application + + For additional details about reserved memory regions see + reserved-memory/reserved-memory.yaml in dtschema project. + +properties: + $nodename: + pattern: '^(qman-fqd|qman-pfdr|bman-fbpr)+$' + + compatible: + enum: + - fsl,qman-fqd + - fsl,qman-pfdr + - fsl,bman-fbpr + +required: + - compatible + +allOf: + - $ref: reserved-memory.yaml + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + qman-fqd { + compatible = "shared-dma-pool"; + size = <0 0x400000>; + alignment = <0 0x400000>; + no-map; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml new file mode 100644 index 000000000000..17016184143f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman-portal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager Portals + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + Portals are memory mapped interfaces to QMan that allow low-latency, lock-less + interaction by software running on processor cores, accelerators and network + interfaces with the QMan + +properties: + compatible: + oneOf: + - const: fsl,qman-portal + - items: + - enum: + - fsl,ls1043-qman-portal + - fsl,ls1046-qman-portal + - fsl,qman-portal-1.2.0 + - const: fsl,qman-portal + + reg: + items: + - description: the cache-enabled region of the portal + - description: the cache-inhibited region of the portal + + interrupts: + maxItems: 1 + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: See pamu.txt. Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN + (FLIODN) + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: See pamu.txt. + + fsl,qman-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: qman channel id. + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The hardware index of the channel. This can also be + determined by dividing any of the channel's 8 work queue + IDs by 8 + + In addition to these properties the qman-portals should have sub-nodes to + represent the HW devices/portals that are connected to the software portal + described here + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +patternProperties: + '^(fman0|fman1|pme|crypto)+$': + type: object + properties: + fsl,liodn: + description: See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + description: See pamu.txt, PAMU property used for dynamic LIODN assignment + + dev-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the particular hardware device that this + portal is connected to. + + additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + qman-portal@0 { + compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; + reg = <0 0x4000>, <0x100000 0x1000>; + interrupts = <104 IRQ_TYPE_EDGE_FALLING 0 0>; + fsl,liodn = <1 2>; + fsl,qman-channel-id = <0>; + + fman0 { + fsl,liodn = <0x21>; + dev-handle = <&fman0>; + }; + + fman1 { + fsl,liodn = <0xa1>; + dev-handle = <&fman1>; + }; + + crypto { + fsl,liodn = <0x41 0x66>; + dev-handle = <&crypto>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml new file mode 100644 index 000000000000..501f06e190c4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan + supports queuing and QoS scheduling of frames to CPUs, network interfaces and + DPAA logic modules, maintains packet ordering within flows. Besides providing + flow-level queuing, is also responsible for congestion management functions such + as RED/WRED, congestion notifications and tail discards. This binding covers the + CCSR space programming model + +properties: + compatible: + oneOf: + - const: fsl,qman + - items: + - enum: + - fsl,ls1043a-qman + - fsl,ls1046a-qman + - const: fsl,qman + reg: + items: + - description: | + Registers region within the CCSR address space + + The QMan revision information is located in the QMAN_IP_REV_1/2 + registers which are located at offsets 0xbf8 and 0xbfc + + interrupts: + items: + - description: The error interrupt + + fsl,qman-portals: + $ref: /schemas/types.yaml#/definitions/phandle + description: ref fsl,qman-port.yaml + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + See pamu.txt, PAMU property used for dynamic LIODN assignment + + clocks: + maxItems: 1 + description: + Reference input clock. Its frequency is half of the platform clock + + memory-region: + maxItems: 2 + description: + List of phandles referencing the QMan private memory nodes (described + below). The qman-fqd node must be first followed by qman-pfdr node. + Only used on ARM Devices connected to a QMan instance via Direct Connect + Portals (DCP) must link to the respective QMan instance. + + fsl,qman: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of phandle and DCP index pairs, to the QMan instance + to which this device is connected via the DCP + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + qman: qman@318000 { + compatible = "fsl,qman"; + reg = <0x318000 0x1000>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 3>; + fsl,liodn = <0x16>; + fsl,qman-portals = <&qportals>; + memory-region = <&qman_fqd &qman_pfdr>; + clocks = <&platform_pll 1>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt deleted file mode 100644 index 5a34f3ab7bea..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt +++ /dev/null @@ -1,134 +0,0 @@ -QorIQ DPAA Queue Manager Portals Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - QMan Portal - - Example - -QMan Portal Node - -Portals are memory mapped interfaces to QMan that allow low-latency, lock-less -interaction by software running on processor cores, accelerators and network -interfaces with the QMan - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,qman-portal-<hardware revision>" - May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Two regions. The first is the cache-enabled region of - the portal. The second is the cache-inhibited region of - the portal - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN - (FLIODN) - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -- cell-index - Usage: Required - Value type: <u32> - Definition: The hardware index of the channel. This can also be - determined by dividing any of the channel's 8 work queue - IDs by 8 - -In addition to these properties the qman-portals should have sub-nodes to -represent the HW devices/portals that are connected to the software portal -described here - -The currently supported sub-nodes are: - * fman0 - * fman1 - * pme - * crypto - -These subnodes should have the following properties: - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - -- dev-handle - Usage: Required - Value type: <phandle> - Definition: The phandle to the particular hardware device that this - portal is connected to. - -EXAMPLE - -The example below shows a (P4080) QMan portals container/bus node with two portals - - qman-portals@ff4200000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0xf 0xf4200000 0x200000>; - - qman-portal@0 { - compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; - reg = <0 0x4000>, <0x100000 0x1000>; - interrupts = <104 2 0 0>; - fsl,liodn = <1 2>; - fsl,qman-channel-id = <0>; - - fman0 { - fsl,liodn = <0x21>; - dev-handle = <&fman0>; - }; - fman1 { - fsl,liodn = <0xa1>; - dev-handle = <&fman1>; - }; - crypto { - fsl,liodn = <0x41 0x66>; - dev-handle = <&crypto>; - }; - }; - qman-portal@4000 { - compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <106 2 0 0>; - fsl,liodn = <3 4>; - cell-index = <1>; - - fman0 { - fsl,liodn = <0x22>; - dev-handle = <&fman0>; - }; - fman1 { - fsl,liodn = <0xa2>; - dev-handle = <&fman1>; - }; - crypto { - fsl,liodn = <0x42 0x67>; - dev-handle = <&crypto>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt b/Documentation/devicetree/bindings/soc/fsl/qman.txt deleted file mode 100644 index ee96afd2af72..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/qman.txt +++ /dev/null @@ -1,187 +0,0 @@ -QorIQ DPAA Queue Manager Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - QMan Node - - QMan Private Memory Nodes - - Example - -QMan Node - -The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan -supports queuing and QoS scheduling of frames to CPUs, network interfaces and -DPAA logic modules, maintains packet ordering within flows. Besides providing -flow-level queuing, is also responsible for congestion management functions such -as RED/WRED, congestion notifications and tail discards. This binding covers the -CCSR space programming model - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,qman" - May include "fsl,<SoC>-qman" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Registers region within the CCSR address space - -The QMan revision information is located in the QMAN_IP_REV_1/2 registers which -are located at offsets 0xbf8 and 0xbfc - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property. The error interrupt - -- fsl,qman-portals - Usage: Required - Value type: <phandle> - Definition: Phandle to this QMan instance's portals - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -- clocks - Usage: See clock-bindings.txt and qoriq-clock.txt - Value type: <prop-encoded-array> - Definition: Reference input clock. Its frequency is half of the - platform clock -- memory-regions - Usage: Required for ARM - Value type: <phandle array> - Definition: List of phandles referencing the QMan private memory - nodes (described below). The qman-fqd node must be - first followed by qman-pfdr node. Only used on ARM - -Devices connected to a QMan instance via Direct Connect Portals (DCP) must link -to the respective QMan instance - -- fsl,qman - Usage: Required - Value type: <prop-encoded-array> - Description: List of phandle and DCP index pairs, to the QMan instance - to which this device is connected via the DCP - -QMan Private Memory Nodes - -QMan requires two contiguous range of physical memory used for the backing store -for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). -This memory is reserved/allocated as a node under the /reserved-memory node. - -For additional details about reserved memory regions see reserved-memory.txt - -The QMan FQD memory node must be named "qman-fqd" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,qman-fqd" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The QMan PFDR memory node must be named "qman-pfdr" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,qman-pfdr" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The following constraints are relevant to the FQD and PFDR private memory: - - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to - 1 GiB - - The alignment must be a muliptle of the memory size - -The size of the FQD and PFDP must be chosen by observing the hardware features -configured via the Reset Configuration Word (RCW) and that are relevant to a -specific board (e.g. number of MAC(s) pinned-out, number of offline/host command -FMan ports, etc.). The size configured in the DT must reflect the hardware -capabilities and not the specific needs of an application - -For additional details about reserved memory regions see reserved-memory.txt - -EXAMPLE - -The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - qman_fqd: qman-fqd { - compatible = "shared-dma-pool"; - size = <0 0x400000>; - alignment = <0 0x400000>; - no-map; - }; - qman_pfdr: qman-pfdr { - compatible = "shared-dma-pool"; - size = <0 0x2000000>; - alignment = <0 0x2000000>; - no-map; - }; - }; - -The example below shows a (P4080) QMan CCSR-space node - - qportals: qman-portals@ff4200000 { - ... - }; - - clockgen: global-utilities@e1000 { - ... - sysclk: sysclk { - ... - }; - ... - platform_pll: platform-pll@c00 { - #clock-cells = <1>; - reg = <0xc00 0x4>; - compatible = "fsl,qoriq-platform-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "platform-pll", "platform-pll-div2"; - }; - ... - }; - - crypto@300000 { - ... - fsl,qman = <&qman, 2>; - ... - }; - - qman: qman@318000 { - compatible = "fsl,qman"; - reg = <0x318000 0x1000>; - interrupts = <16 2 1 3> - fsl,liodn = <0x16>; - fsl,qman-portals = <&qportals>; - memory-region = <&qman_fqd &qman_pfdr>; - clocks = <&platform_pll 1>; - }; - - fman@400000 { - ... - fsl,qman = <&qman, 0>; - ... - }; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml index 2ff174244795..ed1d4aa41b8c 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Low Power SPI (LPSPI) for i.MX maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: /schemas/spi/spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx-thermal.yaml index 808d987bd8d1..337560562337 100644 --- a/Documentation/devicetree/bindings/thermal/imx-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx-thermal.yaml @@ -8,7 +8,6 @@ title: NXP i.MX Thermal maintainers: - Shawn Guo <shawnguo@kernel.org> - - Anson Huang <Anson.Huang@nxp.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml index e7ddaa6c966e..bef0e95e7416 100644 --- a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP i.MX8M Mini Thermal maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> description: | i.MX8MM has TMU IP to allow temperature measurement, there are diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml index 1876fe9555d6..aa756dae512a 100644 --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> $ref: thermal-sensor.yaml# diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml index b6dd98d956f3..75b0e7c70b62 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml @@ -95,6 +95,7 @@ required: - compatible - reg - interrupts + - interrupt-names - clocks - clock-names - power-domains diff --git a/Documentation/devicetree/bindings/timer/sprd,sc9860-timer.yaml b/Documentation/devicetree/bindings/timer/sprd,sc9860-timer.yaml new file mode 100644 index 000000000000..62c6da8bab5a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sprd,sc9860-timer.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sprd,sc9860-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC9860 timer + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +description: + The Spreadtrum SC9860 platform provides 3 general-purpose timers. + These timers can support 32bit or 64bit counter, as well as supporting + period mode or one-shot mode, and they can be a wakeup source + during deep sleep. + +properties: + compatible: + enum: + - sprd,sc9860-timer + - sprd,sc9860-suspend-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: sprd,sc9860-timer + then: + required: + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + timer@40050000 { + compatible = "sprd,sc9860-timer"; + reg = <0 0x40050000 0 0x20>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ext_32k>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt b/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt deleted file mode 100644 index 6d97e7d0f6e8..000000000000 --- a/Documentation/devicetree/bindings/timer/spreadtrum,sprd-timer.txt +++ /dev/null @@ -1,20 +0,0 @@ -Spreadtrum timers - -The Spreadtrum SC9860 platform provides 3 general-purpose timers. -These timers can support 32bit or 64bit counter, as well as supporting -period mode or one-shot mode, and they are can be wakeup source -during deep sleep. - -Required properties: -- compatible: should be "sprd,sc9860-timer" for SC9860 platform. -- reg: The register address of the timer device. -- interrupts: Should contain the interrupt for the timer device. -- clocks: The phandle to the source clock (usually a 32.768 KHz fixed clock). - -Example: - timer@40050000 { - compatible = "sprd,sc9860-timer"; - reg = <0 0x40050000 0 0x20>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ext_32k>; - }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 03e290cb65c3..5d3dc952770d 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -364,6 +364,8 @@ properties: - sparkfun,qwiic-joystick # i2c serial eeprom (24cxx) - st,24c256 + # Sierra Wireless mangOH Green SPI IoT interface + - swir,mangoh-iotport-spi # Ambient Light Sensor with SMBUS/Two Wire Serial Interface - taos,tsl2550 # Temperature Monitoring and Fan Control diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index cd3680dc002f..25a5edeea164 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -46,11 +46,11 @@ properties: clocks: minItems: 7 - maxItems: 11 + maxItems: 9 clock-names: minItems: 7 - maxItems: 11 + maxItems: 9 dma-coherent: true @@ -217,16 +217,14 @@ allOf: then: properties: clocks: - minItems: 11 - maxItems: 11 + minItems: 9 + maxItems: 9 clock-names: items: - - const: core_clk_src - const: core_clk - const: bus_clk - const: bus_aggr_clk - const: iface_clk - - const: core_clk_unipro_src - const: core_clk_unipro - const: core_clk_ice - const: ref_clk @@ -287,7 +285,7 @@ allOf: maxItems: 2 clocks: minItems: 7 - maxItems: 11 + maxItems: 9 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml index 181f0cc5b5bd..36b836d0620c 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX Watchdog Timer (WDT) Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml index 9c50766bf690..a09686b3030d 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller maintainers: - - Anson Huang <Anson.Huang@nxp.com> + - Shawn Guo <shawnguo@kernel.org> + - Sascha Hauer <s.hauer@pengutronix.de> + - Fabio Estevam <festevam@gmail.com> allOf: - $ref: watchdog.yaml# diff --git a/Documentation/devicetree/bindings/watchdog/img,pdc-wdt.yaml b/Documentation/devicetree/bindings/watchdog/img,pdc-wdt.yaml new file mode 100644 index 000000000000..a88a27354505 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/img,pdc-wdt.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/img,pdc-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT) + +maintainers: + - Shresth Prasad <shresthprasad7@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - img,pdc-wdt + + reg: + maxItems: 1 + + clocks: + items: + - description: watchdog counter clock + - description: register interface clock + + clock-names: + items: + - const: wdt + - const: sys + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + watchdog@18102100 { + compatible = "img,pdc-wdt"; + reg = <0x18102100 0x100>; + clocks = <&pdc_wdt_clk>, <&sys_clk>; + clock-names = "wdt", "sys"; + interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt b/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt deleted file mode 100644 index b2fa11fd43de..000000000000 --- a/Documentation/devicetree/bindings/watchdog/imgpdc-wdt.txt +++ /dev/null @@ -1,19 +0,0 @@ -*ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT) - -Required properties: -- compatible : Should be "img,pdc-wdt" -- reg : Should contain WDT registers location and length -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Should contain "wdt" and "sys"; the watchdog counter - clock and register interface clock respectively. -- interrupts : Should contain WDT interrupt - -Examples: - -watchdog@18102100 { - compatible = "img,pdc-wdt"; - reg = <0x18102100 0x100>; - clocks = <&pdc_wdt_clk>, <&sys_clk>; - clock-names = "wdt", "sys"; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; -}; |