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| author | Krzysztof Kozlowski <krzk@kernel.org> | 2026-04-11 11:29:22 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2026-04-11 11:29:22 +0300 |
| commit | 746e195d439a17e0dbe6b6eef080cce66b5aa4ee (patch) | |
| tree | 4ede63188ee31c1145378ec7fadc89a954f627d6 /Documentation/devicetree/bindings | |
| parent | 17ed8fd2fa714bb06c53c5bd88a3948d23fba8f2 (diff) | |
| parent | b0258f69f1e0ed98e8506706da9ef538389b27ea (diff) | |
| download | linux-746e195d439a17e0dbe6b6eef080cce66b5aa4ee.tar.xz | |
Merge tag 'riscv-dt-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V devicetrees for v7.1
Generic:
Add binding coverage for Supm.
Microchip:
Add support for the picgx64 and its curiosity board. This is a PolarFire
SoC without the FPGA.
Add the missing tsu_clk for ptp on the macb on PolarFire SoC and resolve
a long-running problem with gpio interrupts being incorrectly described
on the platform.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC
riscv: dts: microchip: add tsu clock to macb on mpfs
dt-bindings: riscv: Add Supm extension description
riscv: dts: microchip: remove POLARFIRE mention in Makefile
riscv: dts: microchip: add pic64gx and its curiosity kit
dt-bindings: riscv: microchip: document the PIC64GX curiosity kit
dt-bindings: timer: sifive,clint: add pic64gx compatibility
riscv: dts: microchip: add pinctrl nodes for mpfs/icicle kit
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
3 files changed, 33 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index c6ec9290fe07..2b0a8a93bb21 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -262,6 +262,23 @@ properties: ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated to ratified state.") + - const: supm + description: | + The standard Supm extension for pointer masking support in user + mode (U-mode) as ratified at commit d70011dde6c2 ("Update to + ratified state") of riscv-j-extension. + + Supm represents a combination of underlying hardware capability + (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode + software configuration that enables pointer masking for U-mode. + + DO NOT include this property in device trees targeting privileged + system software (S-mode or M-mode). + + This property is only appropriate in device trees provided to + U-mode software where the next-higher-privilege-mode supports + Smnpm or Ssnpm and enables it for U-mode. + - const: svade description: | The standard Svade supervisor-level extension for SW-managed PTE A/D @@ -907,6 +924,16 @@ properties: then: contains: const: b + # Supm depends on Smnpm or Ssnpm + - if: + contains: + const: supm + then: + oneOf: + - contains: + const: smnpm + - contains: + const: ssnpm # Za64rs and Ziccrse depend on Zalrsc or A - if: contains: diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 381d6eb6672e..137a6f413430 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/riscv/microchip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip PolarFire SoC-based boards +title: Microchip SoC-based boards maintainers: - Conor Dooley <conor.dooley@microchip.com> - Daire McNamara <daire.mcnamara@microchip.com> description: - Microchip PolarFire SoC-based boards + Microchip SoC-based boards properties: $nodename: @@ -46,6 +46,9 @@ properties: - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs + - items: + - const: microchip,pic64gx-curiosity-kit + - const: microchip,pic64gx additionalProperties: true diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3bab40500df9..3c16b260db04 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -31,6 +31,7 @@ properties: - enum: - canaan,k210-clint # Canaan Kendryte K210 - eswin,eic7700-clint # ESWIN EIC7700 + - microchip,pic64gx-clint # Microchip PIC64GX - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 - spacemit,k3-clint # SpacemiT K3 |
