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authorLinus Walleij <linus.walleij@linaro.org>2017-05-22 18:27:18 +0300
committerLinus Walleij <linus.walleij@linaro.org>2017-05-22 18:27:18 +0300
commitbdb18d93a79f1c08163f37bef2a517972479e1ed (patch)
tree89b796b91a7f689457e9e5852253105a65c43fa0 /Documentation/devicetree/bindings/pinctrl
parent7f0ff06c1cec4bb2fc039b41943fd23245e3d0ca (diff)
parente25f2af64679581f22b3b9a4681964bd0bb8e417 (diff)
downloadlinux-bdb18d93a79f1c08163f37bef2a517972479e1ed.tar.xz
Merge branch 'ingenic' into devel
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+Ingenic jz47xx pin controller
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
+be used as GPIOs, multiplexed device functions are configured within the
+GPIO port configuration registers and it is typical to refer to pins using the
+naming scheme "PxN" where x is a character identifying the GPIO port with
+which the pin is associated and N is an integer from 0 to 31 identifying the
+pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
+PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
+PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
+total of 192 pins.
+
+
+Required properties:
+--------------------
+
+ - compatible: One of:
+ - "ingenic,jz4740-pinctrl"
+ - "ingenic,jz4770-pinctrl"
+ - "ingenic,jz4780-pinctrl"
+ - reg: Address range of the pinctrl registers.
+
+
+GPIO sub-nodes
+--------------
+
+The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;
+please refer to ../gpio/ingenic,gpio.txt.
+
+
+Example:
+--------
+
+pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,jz4740-pinctrl";
+ reg = <0x10010000 0x400>;
+};